二硫化鉬鐵電場效電晶體於記憶體的應用

Abstract

二維材料在奈米尺度下展現良好電性，如高載子遷移率，使其成為有希望延續摩爾定律的選擇。隨著人工智慧發展，記憶體需求增加，二氧化鉿鐵電材料記憶體引起關注，因其與現代積體電路製程相容，有快速寫入速度與低功耗優點。鐵電場效電晶體(FeFETs)是單電晶體記憶體元件，並具有高保存時間(retention)與高耐久度(endurance)優點，可在未來運用於記憶體內運算(In-Memory Computing)。然而，隨著元件尺度微縮，傳統半導體塊材面臨限制，如載子遷移率因表面散射下降、短通道效應與散熱等挑戰。二維半導體本身無懸浮鍵特性，使通道載子具有高遷移率而不受表面散射影響，與減少漏電流優點。這篇論文研究二維材料通道鐵電場效電晶體，二硫化鉬(MoS2)作為通道，氧化鉿鋯(Hf0.5Zr0.5O2, HZO)作為鐵電閘極介電質。首先，製作以二氧化矽作為閘極介電質之二硫化鉬電晶體並進行電性分析，隨後，將氧化層替換為氧化鉿鋯，製作鐵電場效電晶體並進行電性分析。 第一部分，製作二硫化鉬電晶體，使用高摻雜矽基板作為底閘極，二氧化矽作為閘極氧化層，鉻/金作為源極/汲極金屬，在充滿氮氣的手套箱環境中利用機械式剝離法分離塊材二硫化鉬，並用乾式轉移將薄膜轉移到元件上。二硫化鉬厚度100 奈米之電晶體展現良好電流開關比105(過驅電壓1.1 伏特)，與次臨界擺幅150 mV/dec。另一元件二硫化鉬厚度20 奈米之電晶體，額外使用石墨烯作為源極/汲極接觸金屬，電流開關比提升至106，石墨烯功函數隨電壓上升而下降，與二硫化鉬形成較好的歐姆接觸。此外，元件次臨界擺幅提升至90 mV/dec，石墨烯是狄拉克(Dirac)材料，減少電子密度在費米能階之上的分佈，使電子注入通道更集中。 第二部分，分別在金屬-鐵電(介電層)-半導體(MF(I)S)電容結構與二維材料鐵電電晶體中比較四種不同鐵電氧化鉿鋯與氧化鋁堆疊。對於電容，氧化鋁堆疊在氧化鉿鋯上展現最大剩餘極化值，在退火時上方氧化鋁有助於形成氧化鉿鋯鐵電特性。對於二維材料鐵電電晶體，只有氧化鋁堆疊在氧化鉿鋯上的元件展現逆時針ID-VG，對應其鐵電電晶體特性。其他元件展現順時針ID-VG，歸因於閘極電壓掃描時於氧化層/半導體介面發生電荷捕捉效應，較高濃度的介面電荷抵消鐵電遲滯現象。

Two-dimensional (2D) materials exhibit excellent electrical properties at a nanometer scale, such as high carrier mobility, making them a promising candidate to extend Moore’s Law. With the growing demand for memory driven by advancements in artificial intelligence (AI), HfO2-based ferroelectric materials are considered promising candidate for non-volatile memory due to their VLSI compatibility, fast write speeds, and low power consumption. FeFETs, as one-transistor (1T) memory device with high retention and endurance, hold potential for future in-memory computing. However, as devices are further scaled down, bulk semiconductors face limitations, such as decreased carrier mobility due to surface scattering, short-channel effects, and heat dissipation challenges. 2D semiconductors with dangle-bond-free nature allow these materials to maintain high carrier mobility and reduce the leakage current. This study focuses on 2D-based FeFETs using MoS2 as a channel material and Hf0.5Zr0.5O2 (HZO) as a ferroelectric gate dielectric. First, MoS2 MOSFETs with SiO2 as a dielectric layer are fabricated and characterized. Then replacing the oxide with ferroelectric HZO to fabricate FeFETs and investigate their device characteristics. In the first part, 2D FETs were fabricated with highly doped Si substrates serving as a bottom gate, followed by the deposition of SiO2 as a gate dielectric and Cr/Au as electrodes to the source/drain (S/D). Then MoS2 thin films are mechanically exfoliated and dry transferred onto the sample in a nitrogen-filled glove box to finish the processes. 2D FET with 100 nm-thick MoS2 achieved a high current on/off ratio of 105 under an overdrive voltage 1.1 V and a subthreshold swing (SS) 150 mV/dec. Additionally, another device with MoS2 20 nm-thick, using graphene as the S/D contact, the on/off ratio is improved to 106. The workfunction of graphene decreases as the voltage increases, forming a better Ohmic contact with MoS2. Furthermore, the SS is improved to 90 mV/dec, which might be attributed to the density-state switching by using graphene as a Dirac source. In the second part, four different oxide stacks of Al2O3 and ferroelectric HZO are investigated in metal-ferroelectric(interlayer)-semiconductor (MF(I)S) capacitors and 2D FeFETs. For the capacitors, the stack with Al2O3 on HZO shows higher remnant polarization. The presence of the cap Al2O3 during rapid thermal annealing (RTA) step leads to an enhancement of the ferroelectricity. For 2D FeFETs, only the stack of Al2O3 on HZO showed counterclockwise hysteresis loop of I-V characteristics, a signature of ferroelectric switching. Other devices show clockwise hysteresis loops, which is attributed to the charge trapping effects at the oxide/semiconductor interface during the gate sweeps. A higher density of charge trapping may counterbalance the ferroelectricity.