一個使用一階數位誤差回授截斷器之三階連續時間縮放式類比數位轉換器

Abstract

本論文提出了一個三階連續時間的縮放式類比數位轉換器，並採用了一階數位誤差回授截斷器。縮放式類比數位轉換器的架構結合逐次逼近類比數位轉換器作為第一級的類比數位轉換器，三角積分調變轉換器作為第二級的類比數位轉換器。透過逐次逼近類比數位轉換器提供的參考電壓縮小輸入訊號範圍，使三角積分調變轉換器只需要處理小振幅訊號。因此，數位誤差回授截斷器可以在不降低類比數位轉換器的最大穩定振幅下，整合到縮放式類比數位轉換器中，並且相對於類比噪聲耦合架構具有一定的競爭力，因數位信號較不易受製程變異影響。此外，數位誤差回授截斷器提供額外的噪聲整形階數，類似於噪聲耦合架構提供的效果，並有助於提升所提出的類比數位轉換器的頻寬。 第一級積分器中的運算轉導放大器需具備低功耗、低噪聲與寬頻寬。為達到設計需求，電流再利用技術可將運算轉導放大器的輸入級功耗減少一半、而斬波技術則可抑制96%的頻帶內噪聲。此外，前饋技術可稍微提升放大器的單位增益頻率。 當相應的數位回授碼實現於數位誤差回授截斷器中時，多位元回授可成功整合進所提出的縮放式類比數位轉換器，而不會產生嚴重的諧波失真。此外，多位元回授可透過抑制量化噪聲並降低回授濾波器的輸出擺幅，來提升類比數位轉換器的最大穩定振幅及線性度 此次晶片使用台積電180奈米CMOS製程實現了兩顆晶片，操作頻率在一千萬赫茲，訊號頻寬為二十千赫茲。當三角積分調變轉換器使用一位元回授時，類比數位轉換器達到99.72 dB的訊號對雜訊失真比，104.6 dB的動態範圍，以及1.629 毫瓦的功率，對應的Scherier動態範圍品質因數為175.49 dB。而當三角積分調變轉換器使用二位元回授時，類比數位轉換器達到101.25 dB的訊號對雜訊失真比，108.0 dB的動態範圍，以及1.562 毫瓦的功率，對應的Scherier動態範圍品質因數為179.07 dB。

This work presents a 3rd-order continuous-time zoom analog-to-digital converter (ADC) with a 1st-order digital error feedback truncator. The zoom ADC combines a successive approximation register (SAR) ADC as the first stage and a delta-sigma modulator (DSM) ADC as the second stage. By performing a zoom-in on the input signal with the reference voltage provided by the SAR ADC, the DSM ADC processes only small signal amplitudes. Thus, the digital error feedback truncator can be integrated into the zoom ADC without degrading the maximum stable amplitude (MSA) of the ADC, making it a competitive alternative to the analog noise-coupled architecture since digital signals are less affected by process variations. Furthermore, the digital error feedback truncator provides an additional noise-shaping order, similar to the effect provided by the noise-coupled architecture, and helps extend the proposed ADC bandwidth. The OTA in the first-stage integrator requires low power consumption, low noise, and wide bandwidth. To meet these demands, the current-reuse technique reduces the power consumption of the input stage of the OTA by half, while the chopper technique suppresses in-band noise contribution by 96%. Furthermore, the feedforward technique slightly extends the unity-gain frequency of the OTA. With a corresponding digital feedback code implemented in the digital error feedback truncator, multi-bit feedback can be successfully incorporated into the proposed ADC without inducing severe harmonic tones. Additionally, multi-bit feedback increases the MSA and the linearity of the ADC by suppressing quantization noise and reducing the output swing of the loop filter. Two prototype chips were fabricated in the TSMC 180 nm CMOS process, operating at a 10 MHz sampling frequency and a 20 kHz signal bandwidth. This work achieves 99.72 dB SNDR, 104.6 dB DR, and 1.629 mW power consumption with 1-bit feedback from the DSM loop, with a FoMS,DR of 175.49 dB. With 2-bit feedback, the ADC reaches 101.25 dB SNDR, 108.0 dB DR, and 1.562 mW power consumption, with a FoMS,DR of 179.07 dB.