鍺與磷原子擴散對奈米片場效電晶體的影響

Abstract

奈米片場效電晶體 (Nanosheet Field-Effect Transistors, NSFETs) 因其優異的性能已成為下一代技術節點的關鍵邏輯元件。然而，奈米片場效電晶體的多層異質結構對電晶體的性能產生非常大的挑戰，例如原子擴散可能會影響電晶體的遷移率，本論文將探討磷與鍺的擴散對奈米片場效電晶體的影響。 第二章介紹了鰭式場效電晶體 (FinFET) 和奈米片場效電晶體的製程流程，並展示了低次臨界斜率 (71 mV/dec)、低漏電流 (小於 1 nA/μm) 以及改善的汲極誘導能障降低 (3 mV/V)。比較進行擴散與未擴散步驟的奈米片場效電晶體，當元件進行900度擴散步驟後，元件性能顯著劣化，例如開關電流比大幅下降、次臨界斜率增加以及電子遷移率下降。 第三章研究磷與鍺原子擴散個別對平面電晶體的影響，成長矽鍺磊晶層後，進行600至800度的擴散步驟後，再將矽鍺磊晶層移除。結果顯示磷與鍺原子的擴散皆會導致電子遷移率下降。此外，磷原子會降低臨界電壓並增加漏電流，而鍺原子則對次臨界斜率產生負面影響。這些研究結果突顯了原子擴散對奈米片場效電晶體性能的負面影響，及在製造過程中控制原子擴散的重要性，以確保奈米片場效電晶體的最佳性能與穩定性。

Nanosheet Field-Effect Transistors (NSFETs) have become a key logic device for next-generation technology nodes due to their superior performance. However, the multilayer structure in a NSFET poses challenges, such as atomic diffusion, which can impact transistor performance by degrading electron mobility. This thesis investigates the diffusion effects of phosphorus and germanium on NSFETs. Chapter 2 introduces the fabrication processes of FinFET and NSFETs and demonstrates low subthreshold swing (71 mV/dec), reduced leakage current (below 1 nA/μm), and improved drain-induced barrier lowering (3 mV/V). By performing diffusion steps at 900 oC, the device performance is degraded significantly, such as a much reduced of on/off current ratio, increased SS, and reduced electron mobility. Chapter 3 investigate the effects of phosphorus and germanium atoms on planar Si MOSFETs. SiGe epitaxial layers are epitaxially grown followed by diffusion steps at 600 to 800 °C and selective etching is performed to etch the SiGe layers. The results show that the diffusion of phosphorus and germanium atoms leads to reduced electron mobility. Furthermore, phosphorus lowers the threshold voltage and increases the leakage current, while germanium adversely impacts the subthreshold swing. These findings highlight the detrimental impact of phosphorus and germanium on the NSFET performance, emphasizing the need for precise control of atomic diffusion in the manufacturing processes to ensure optimal device performance and stability.