請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96951完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李峻霣 | zh_TW |
| dc.contributor.advisor | Jiun-Yun Li | en |
| dc.contributor.author | 陳恩 | zh_TW |
| dc.contributor.author | En Chen | en |
| dc.date.accessioned | 2025-02-25T16:12:08Z | - |
| dc.date.available | 2025-02-26 | - |
| dc.date.copyright | 2025-02-25 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-01-25 | - |
| dc.identifier.citation | [1] R. R. Schaller, "Moore's law: Past, present, and future," IEEE Spectrum, vol. 34, no. 6, pp. 52–59, Jun. 1997.
[2] C. Märtin, "Post-Dennard scaling and the final years of Moore’s law consequences for the evolution of multicore-architectures," Informatik und Interaktive Systeme, Sep. 2014. [3] M. Roser, H. Ritchie, and E. Mathieu, "What is Moore's law?," Our World in Data, Apr. 2023. [Online]. Available: https://ourworldindata.org/moores-law [4] T. Ghani et al., "A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors," in Proc. IEEE Int. Electron Devices Meeting (IEDM), Washington, DC, USA, 2003. [5] M. Chudzik et al., "High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing," in Proc. IEEE Symp. VLSI Technol., Kyoto, Japan, 2007. [6] Y. Song et al., "Mobility enhancement technology for scaling of CMOS devices: Overview and status," J. Electron. Mater., vol. 40, no. 3, pp. 1584–1612, Mar. 2011. [7] S. Gai, "The end of Dennard scaling," Mar. 2020. [Online]. Available: https://silvanogai.github.io/posts/dennard/ [8] C. W. Pearce and D. S. Yaney, "Short-channel effects in MOSFET's," IEEE Electron Device Lett., vol. 6, no. 7, pp. 326–328, Jul. 1985. [9] D. Hisamoto et al., "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320–2325, Dec. 2000. [10] S. Vidya, S. V. Kamat, A. R. Khan, and V. Venkatesh, "3D FinFET for next generation nano devices," in Proc. Int. Conf. Current Trends Converging Technol. (ICCTCT), Coimbatore, India, 2018. [11] "Smaller, better, faster: Imec presents chip scaling roadmap," Imec, Feb. 2023. [Online]. Available: https://www.imec-int.com/en/articles/smaller-better-faster-imec-presents-chip-scaling-roadmap [12] L. Wu, "The next generation of gate-all-around transistors," Nat. Electron., vol. 6, no. 7, p. 469, Jul. 2023. [13] U. K. Das and T. K. Bhattacharyya, "Opportunities in device scaling for 3-nm node and beyond: FinFET versus GAA-FET versus UFET," IEEE Trans. Electron Devices, vol. 67, no. 6, pp. 2633–2638, Jun. 2020. [14] A. Veloso et al., "Nanowire and nanosheet FETs for ultra-scaled, high-density logic and memory applications," in Proc. Joint Int. EUROSOI Workshop and Int. Conf. Ultimate Integration Silicon (EUROSOI-ULIS), Grenoble, France, 2019. [15] S.-D. Kim et al., "Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond," in Proc. IEEE SOI-3D-Subthreshold Microelectron. Technol. Unified Conf. (S3S), Rohnert Park, CA, USA, 2015. [16] R. R. Das, T. R. Rajalekshmi, and A. James, "FinFET to GAA MBCFET: A review and insights," IEEE Access, vol. 12, pp. 50556–50577, 2024. [17] Y.-C. Huang, M.-H. Chiang, S.-J. Wang, and J. G. Fossum, "GAAFET versus pragmatic FinFET at the 5nm Si-based CMOS technology node," IEEE J. Electron Devices Soc., vol. 5, no. 3, pp. 164–169, May 2017. [18] S. Barraud et al., "7-levels-stacked nanosheet GAA transistors for high performance computing," in Proc. IEEE Symp. VLSI Technol., Honolulu, HI, USA, 2020. [19] C.-L. Chu et al., "Ge/Si multilayer epitaxy and removal of dislocations from Ge-nanosheet-channel MOSFETs," Sci. Rep., vol. 12, no. 1, p. 959, Jan. 2022. [20] N. Loubet et al., "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," in Proc. Symp. VLSI Technol., Kyoto, Japan, 2017. [21] I. Lauer et al., "Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance," in Proc. Symp. VLSI Technol., Kyoto, Japan, 2015. [22] N. Loubet et al., "A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around nanosheet devices," in Proc. IEEE Int. Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019. [23] S.-M. Kim et al., "A study on selective Si₀.₈Ge₀.₂ etch using polysilicon etchant diluted by H₂O for three-dimensional Si structure application," Proc. Electrochem. Soc., vol. 3, no. 3, pp. 81–86, 2003. [24] J. Li et al., "Study of selective isotropic etching Si₁₋ₓGeₓ in process of nanowire transistors," J. Mater. Sci.: Mater. Electron., vol. 31, pp. 134–143, Jan. 2020. [25] R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 3rd ed., Hoboken, NJ, USA: Wiley, 2003. [26] S. M. Sze, Y. Li, and K. K. Ng, Physics of Semiconductor Devices, 4th ed., Hoboken, NJ, USA: Wiley, 2021. [27] I. Synopsys, Sentaurus Device User Guide, version I-2013.12, Mountain View, CA, USA, 2013. [28] S. Reboh et al., "Imaging, modeling and engineering of strain in gate-all-around nanosheet transistors," in Proc. IEEE Int. Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019. [29] N. R. Zangenberg et al., "Boron and phosphorus diffusion in strained and relaxed Si and SiGe," J. Appl. Phys., vol. 94, no. 6, pp. 3883–3890, Sep. 2003. [30] J. S. Christensen et al., "Diffusion of phosphorus in relaxed Si₁₋ₓGeₓ films and strained Si/Si₁₋ₓGeₓ heterostructures," J. Appl. Phys., vol. 94, no. 10, pp. 6533–6540, Nov. 2003. [31] Y. Liu, M. Luisier, A. Majumdar, D. A. Antoniadis, and M. S. Lundstrom, "On the interpretation of ballistic injection velocity in deeply scaled MOSFETs," IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 994–1001, Apr. 2012. [32] O. Badami et al., "An improved surface roughness scattering model for bulk, thin-body, and quantum-well MOSFETs," IEEE Trans. Electron Devices, vol. 63, no. 6, pp. 2306–2312, Jun. 2016. [33] N. R. Zangenberg et al., "Ge self-diffusion in epitaxial Si₁₋ₓGeₓ layers," Phys. Rev. Lett., vol. 87, no. 12, p. 125901, Aug. 2001. [34] S. Werner et al., "Doping-and carrier concentration profile characterisation of highly phosphorus-doped emitters," in Proc. 25th Eur. Photovoltaic Solar Energy Conf. and Exhib., Valencia, Spain, 2010. [35] S. M. Sze, Y. Li, and K. K. Ng, Physics of Semiconductor Devices, 4th ed., Hoboken, NJ, USA: Wiley, 2021. [36] G. Masetti, M. Severi, and S. Solmi, "Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon," IEEE Trans. Electron Devices, vol. 30, no. 7, pp. 764–769, Jul. 1983. [37] N. Collaert and K. De Meyer, "Effect of the Ge-mole fraction on the subthreshold slope and leakage current of vertical Si/Si₁₋ₓGeₓ MOSFETs," Solid-State Electron., vol. 43, no. 12, pp. 2173–2180, 1999. [38] M. V. Fischetti and S. E. Laux, "Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys," J. Appl. Phys., vol. 80, no. 4, pp. 2234–2252, Aug. 1996. [39] S. Kim, S. H. Lee, I. H. Jo, et al., "Influence of growth temperature on dielectric strength of Al₂O₃ thin films prepared via atomic layer deposition at low temperature," Sci. Rep., vol. 12, Mar. 2022. [40] J. Tao et al., "Extrinsic and intrinsic frequency dispersion of high-k materials in capacitance-voltage measurements," Materials, vol. 5, pp. 1005–1032, Jun. 2012. [41] W. Kern and D. A. Puotinen, "Cleaning solutions based on hydrogen peroxide for use in silicon semiconductor technology," RCA Rev., vol. 31, pp. 187–206, Jun. 1970. [42] X. Yuan et al., "Gate-induced-drain-leakage current in 45-nm CMOS technology," IEEE Trans. Device Mater. Reliab., vol. 8, no. 3, pp. 501–508, Sep. 2008. [43] A. D. R. Ribeiro, G. V. Araujo, J. A. Martino, and P. G. D. Agopian, "Trade-off between channel length and mechanical stress in the operational transconductance amplifier designed with SOI FinFET," in Proc. 37th Symp. Microelectron. Technol. Devices (SBMicro), Rio de Janeiro, Brazil, 2023. [44] H. Mohammadi et al., "Analytical modeling and simulation of a fully depleted three-gate silicon MESFET on SOI material," J. Comput. Electron., vol. 18, pp. 91–102, Jan. 2019. [45] N. E. I. Boukortt et al., "Effects of varying the fin width, fin height, gate dielectric material, and gate length on the DC and RF performance of a 14-nm SOI FinFET structure," Electronics, vol. 11, no. 1, p. 91, 2021. [46] S.-E. Huang, C.-L. Yu, and P. Su, "Investigation of fin-width sensitivity of threshold voltage for InGaAs and Si negative-capacitance FinFETs considering quantum-confinement effect," IEEE Trans. Electron Devices, vol. 66, no. 6, pp. 2538–2543, Jun. 2019. [47] M. J. Kumar and G. V. Reddy, "Diminished short channel effects in nanoscale double-gate silicon-on-insulator metal–oxide–semiconductor field-effect-transistors due to induced back-gate step potential," Jpn. J. Appl. Phys., vol. 44, no. 9R, p. 6508, Sep. 2005. [48] M. F. Al-Mistarihi, A. Rjoub, and N. R. Al-Taradeh, "Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor," in Proc. 2013 25th Int. Conf. Microelectron. (ICM), Beirut, Lebanon, 2013. [49] I. Synopsys, Sentaurus Device User Guide, version I-2013.12, Mountain View, CA, USA, 2013. [50] S. Reboh et al., "Imaging, modeling and engineering of strain in gate-all-around nanosheet transistors," in Proc. IEEE Int. Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019. [51] N. R. Zangenberg et al., "Boron and phosphorus diffusion in strained and relaxed Si and SiGe," J. Appl. Phys., vol. 94, no. 6, pp. 3883–3890, Sep. 2003. [52] J. S. Christensen et al., "Diffusion of phosphorus in relaxed Si₁₋ₓGeₓ films and strained Si/Si₁₋ₓGeₓ heterostructures," J. Appl. Phys., vol. 94, no. 10, pp. 6533–6540, Nov. 2003. [53] Y. Liu et al., "On the interpretation of ballistic injection velocity in deeply scaled MOSFETs," IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 994–1001, Apr. 2012. [54] O. Badami et al., "An improved surface roughness scattering model for bulk, thin-body, and quantum-well MOSFETs," IEEE Trans. Electron Devices, vol. 63, no. 6, pp. 2306–2312, Jun. 2016. [55] N. R. Zangenberg et al., "Ge self-diffusion in epitaxial Si₁₋ₓGeₓ layers," Phys. Rev. Lett., vol. 87, no. 12, p. 125901, Aug. 2001. [56] S. Werner et al., "Doping-and carrier concentration profile characterisation of highly phosphorus-doped emitters," in Proc. 25th Eur. Photovoltaic Solar Energy Conf. and Exhib., Valencia, Spain, 2010. [57] S. M. Sze, Y. Li, and K. K. Ng, Physics of Semiconductor Devices, 4th ed., Hoboken, NJ, USA: Wiley, 2021. [58] G. Masetti, M. Severi, and S. Solmi, "Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon," IEEE Trans. Electron Devices, vol. 30, no. 7, pp. 764–769, Jul. 1983. [59] N. Collaert and K. De Meyer, "Effect of the Ge-mole fraction on the subthreshold slope and leakage current of vertical Si/Si₁₋ₓGeₓ MOSFETs," Solid-State Electron., vol. 43, no. 12, pp. 2173–2180, 1999. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96951 | - |
| dc.description.abstract | 奈米片場效電晶體 (Nanosheet Field-Effect Transistors, NSFETs) 因其優異的性能已成為下一代技術節點的關鍵邏輯元件。然而，奈米片場效電晶體的多層異質結構對電晶體的性能產生非常大的挑戰，例如原子擴散可能會影響電晶體的遷移率，本論文將探討磷與鍺的擴散對奈米片場效電晶體的影響。
第二章介紹了鰭式場效電晶體 (FinFET) 和奈米片場效電晶體的製程流程，並展示了低次臨界斜率 (71 mV/dec)、低漏電流 (小於 1 nA/μm) 以及改善的汲極誘導能障降低 (3 mV/V)。比較進行擴散與未擴散步驟的奈米片場效電晶體，當元件進行900度擴散步驟後，元件性能顯著劣化，例如開關電流比大幅下降、次臨界斜率增加以及電子遷移率下降。 第三章研究磷與鍺原子擴散個別對平面電晶體的影響，成長矽鍺磊晶層後，進行600至800度的擴散步驟後，再將矽鍺磊晶層移除。結果顯示磷與鍺原子的擴散皆會導致電子遷移率下降。此外，磷原子會降低臨界電壓並增加漏電流，而鍺原子則對次臨界斜率產生負面影響。這些研究結果突顯了原子擴散對奈米片場效電晶體性能的負面影響，及在製造過程中控制原子擴散的重要性，以確保奈米片場效電晶體的最佳性能與穩定性。 | zh_TW |
| dc.description.abstract | Nanosheet Field-Effect Transistors (NSFETs) have become a key logic device for next-generation technology nodes due to their superior performance. However, the multilayer structure in a NSFET poses challenges, such as atomic diffusion, which can impact transistor performance by degrading electron mobility. This thesis investigates the diffusion effects of phosphorus and germanium on NSFETs. Chapter 2 introduces the fabrication processes of FinFET and NSFETs and demonstrates low subthreshold swing (71 mV/dec), reduced leakage current (below 1 nA/μm), and improved drain-induced barrier lowering (3 mV/V). By performing diffusion steps at 900 oC, the device performance is degraded significantly, such as a much reduced of on/off current ratio, increased SS, and reduced electron mobility.
Chapter 3 investigate the effects of phosphorus and germanium atoms on planar Si MOSFETs. SiGe epitaxial layers are epitaxially grown followed by diffusion steps at 600 to 800 °C and selective etching is performed to etch the SiGe layers. The results show that the diffusion of phosphorus and germanium atoms leads to reduced electron mobility. Furthermore, phosphorus lowers the threshold voltage and increases the leakage current, while germanium adversely impacts the subthreshold swing. These findings highlight the detrimental impact of phosphorus and germanium on the NSFET performance, emphasizing the need for precise control of atomic diffusion in the manufacturing processes to ensure optimal device performance and stability. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-02-25T16:12:08Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-02-25T16:12:08Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 ii
摘要 iii Abstract iv 目次 v 圖次 vii 表次 xiii 第1章 引言 1 1.1 摩爾定律 1 1.2 環繞閘極場效電晶體 5 1.3 論文架構 7 第2章 奈米片場效電晶體 9 2.1 文獻回顧 9 2.1.1 蝕刻技術改善 11 2.1.2 奈米片場效電晶體製程及其結構的改善 13 2.2 鰭式場效電晶體與奈米片場效電晶體的製作 16 2.2.1 鰭式場效電晶體的製程 16 2.2.2 奈米片場效電晶體的製程 18 2.3 鰭式場效電晶體與奈米片場效電晶體量測與分析 21 2.3.1 鰭式場效電晶體量測與分析 22 2.3.2 奈米片場效電晶體量測與分析 26 2.3.3 奈米片場效電晶體與鰭式場效電晶體比較 30 2.3.4 奈米片場效電晶體經高溫擴散的影響 35 2.4 小結 38 第3章 鍺或磷擴散對於n-型矽場效電晶體的影響 40 3.1 磷原子擴散對於場效電晶體的影響 40 3.1.1 實驗設計 42 3.1.2 平面式場效電晶體的製作 44 3.1.3 選擇性蝕刻實驗 47 3.2 磷與鍺原子經退火實際分布結果與分析 50 3.2.1 利用科技電腦輔助設計模擬磷原子於矽基板的分布 52 3.2.2 實際磷與鍺原子經退火後於矽基板的分布 54 3.3 磷與鍺原子對於電晶體影響 57 3.3.1 利用科技電腦輔助設計模擬磷原子對電晶體電性影響分析 57 3.3.2 實際磷與鍺原子對於n-型電晶體影響分析 60 3.4 鍺原子擴散對於電晶體影響 64 3.4.1 實際鍺原子擴散對於n-型電晶體影響分析 64 3.4.2 磷與鍺原子擴散與僅鍺原子擴散的影響 67 3.5 小結 69 第4章 結論 71 4.1 結論 71 4.2 未來工作 72 參考文獻 73 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 奈米片場效電晶體 (NSFET) | zh_TW |
| dc.subject | 環繞式閘極 (GAA) 結構 | zh_TW |
| dc.subject | 原子擴散 | zh_TW |
| dc.subject | 庫侖散射 | zh_TW |
| dc.subject | 合金散射 | zh_TW |
| dc.subject | 電子遷移率 | zh_TW |
| dc.subject | Electron Mobility | en |
| dc.subject | Gate-All-Around (GAA) Structure | en |
| dc.subject | Nanosheet Field-Effect Transistor (NSFET) | en |
| dc.subject | Atomic Diffusion | en |
| dc.subject | Coulomb Scattering | en |
| dc.subject | Alloy Scattering | en |
| dc.title | 鍺與磷原子擴散對奈米片場效電晶體的影響 | zh_TW |
| dc.title | Effects of Germanium and Phosphorus Diffusion on Nanosheet Field-Effect Transistors | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 溫政彥;李敏鴻;李耀仁 | zh_TW |
| dc.contributor.oralexamcommittee | Cheng-Yen Wen;Min-Hung Lee;Yao-Jen Lee | en |
| dc.subject.keyword | 環繞式閘極 (GAA) 結構,奈米片場效電晶體 (NSFET),原子擴散,庫侖散射,合金散射,電子遷移率, | zh_TW |
| dc.subject.keyword | Gate-All-Around (GAA) Structure,Nanosheet Field-Effect Transistor (NSFET),Atomic Diffusion,Coulomb Scattering,Alloy Scattering,Electron Mobility, | en |
| dc.relation.page | 80 | - |
| dc.identifier.doi | 10.6342/NTU202500267 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2025-01-26 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2028-01-23 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-113-1.pdf 此日期後於網路公開 2028-01-23 | 3.89 MB | Adobe PDF |
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