四族半導體異質結構量子點之元件模擬

Abstract

四族半導體因其在高濃度同位素材料中的長退相干時間及與VLSI製造科技的相容性，成為有潛力實現自旋量子位元(qubit)的方法之一。由閘極所形成之量子點(gate-defined QD)是製造半導體量子位元的最常用方法。通過異質結構來禁止載子面外方向的移動，將其限制在準二維系統中，而上方閘極進一步限制載子在面內方向的運動，形成可容納數個載子的量子點，進行自旋操作與讀出。然而，在大規模量子點陣列中，串擾電容效應阻礙了每個量子點電位的獨立控制。目前，很少有實驗或研究著重在不同量子點設計中的閘極間的串擾問題，因此對不同結構設計的半導體量子點進行電特性的模擬比較有其必要性。 本論文基於模擬的分析比較不同設計量子點的電特性。透過使用COMSOL計算每個閘極的電容，並通過電容模型結合主方程式來模擬出量子點的特徵，包括庫倫阻隔和電荷穩定圖。接著，對閘極配置與間隔層厚度等諸多參數對量子點電特性的影響進行研究。在矽基量子點中，通過將吸引閘極(plunger gate)設置在阻隔閘極(barrier gate)之下、增加吸引閘極與阻隔閘極的長度比、引入限制閘極(confinement gate)，減少了阻隔閘極偏壓對量子點的影響，進而改善了吸引閘極控制的獨立性。在矽/矽鍺量子點中，增厚矽鍺間隔層提高了電荷穩定性，但降低了吸引閘極控制的獨立性，導致鄰近量子點彼此的串擾增強。 對於鍺基量子點，通過經驗贗勢法計算了應變鍺與鍺錫量子阱中的等效質量與能障高低。在這些量子點中，較厚的間隔層提高了電荷穩定性，但會降低吸引閘的獨立控制性，這與矽基量子點的趨勢相似。比較矽基和鍺基量子點發現，間隔層的介電特性顯著影響電荷穩定性，而不影響吸引閘極與阻隔閘極之間的控制比。這一分析表明，與材料選擇相比，閘極配置在實現獨立閘極控制方面有著更明顯的影響。

Group-IV semiconductors are a promising platform for spin-based quantum bit (qubit) devices owing to their long decoherence times in isotopically enriched materials and compatibility with VLSI manufacturing technology. Gate-defined quantum dots (QDs) are widely used devices for realizing qubits in semiconductors. Carrier confinement along the z-direction in these devices is achieved through heterostructures, which restrict out-of-plane motion to form a quasi-two-dimensional system. Top gates then confine carriers in the in-plane directions, creating a QD that can host one or a few electrons for spin manipulation and readout. However, in large-scale QD arrays, cross-capacitance effects hamper the independent control of each QD potential. However, limited research has explored the cross-talk issues across different QD designs, making it important to simulate and compare the electrical properties of various QD configurations. This thesis presents a simulation-based analysis of the electrical properties of different QDs. The simulation process uses COMSOL to calculate the capacitance of each gate and combines the capacitance model with the master equation to characterize electrical properties of QD, such as Coulomb blockade and stability diagram. The influence of gate configuration and spacer thickness on QD electrical property are investigated. In Si-based QDs, placing the plunger gate beneath the barrier gates, increasing the plunger-to-barrier gate length ratio, or incorporating confinement gates improve control capability of the plunger gates by reducing the impact from barrier gate biases. Increasing the SiGe spacer thickness in Si/SiGe QDs also enhances charge stability, but weakens the control by the plunger gates, leading to increased cross-talk between neighboring QDs. For Ge-based QDs, effective masses and band offsets in strained Ge and GeSn quantum wells are computed using the empirical pseudopotential method. In these devices, thicker spacers improve charge stability, but at the cost of reduced plunger gate control—similar to trends observed in Si-based QDs. Comparing Si- and Ge-based QDs, the dielectric of the spacer significantly affects charge stability, but have little effect on the difference of the control ability between the plunger and barrier gates. This analysis indicates that gate configuration is more critical for achieving independent gate control than the material choice.