基於數位背景校正之小數除頻器設計

Abstract

本論文提出了一種具全數位背景校準功能的分數除頻器的設計與實現。一種新穎架構的不定時間數位轉換器被設計，實現低面積、高精確度的轉換，用於數位至時間轉換器的精確校準，且無需額外的類比電路。本作品基於不定時間數位轉換器的運作機制，開發了一套校準演算法於數位電路中執行，能夠在不中斷分數除頻操作的情況下實現背景校準。 本作品使用90奈米的CMOS製程製造，核心面積為0.021平方公釐，支援輸出頻率範圍為2.7兆赫至357兆赫，並採用21位元的分數編碼，使其輸出解析度可達25赫茲。量測結果顯示，在輸出頻率為269兆赫時，晶片整體功耗為4.23毫瓦，當背景校正完成後，分數突波可以從原先的-38.1dBc降低至-67.6dBc，整體抖動達到258飛秒。本作品提出的小數除頻器達到了-245.5dB的抖動量性能指標，展現出在分數除頻領域的領先性能表現。

In this thesis, we present the design and implementation of a fractional output divider (FOD) with all-digital background calibration. An indeterminate time-to-digital converter (ITDC) is designed to achieve high-resolution time-span digitization with minimal area overhead, achieving precise calibration of the digital-to-time converter (DTC) without additional analog circuits. Furthermore, a calibration algorithm is developed based on ITDC’s operation, which entirely conducts in digital domain, facilitating background calibration without interrupting the FOD's operation. Fabricated in a 90nm CMOS process with a core area of 0.021 mm^2, the FOD supports an output frequency range from 2.7 MHz to 357 MHz with a resolution of 25 Hz with 21-bit fractional codes. Operating at an output frequency of 269 MHz, the power consumption is measured at 4.23 mW. Measurement results show a reduction in fractional spurs from -38.1 dBc to -67.6 dBc and an integrated jitter of 258 fs after calibration. The proposed FOD achieves a jitter figure-of-merit (FoM) of -245.5 dB, demonstrating its state-of-the-art performance in fractional output division.