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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | zh_TW |
| dc.contributor.advisor | Tsung-Hsien Lin | en |
| dc.contributor.author | 陳暐翰 | zh_TW |
| dc.contributor.author | Wei-Han Chen | en |
| dc.date.accessioned | 2025-02-19T16:38:36Z | - |
| dc.date.available | 2025-02-20 | - |
| dc.date.copyright | 2025-02-19 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-01-14 | - |
| dc.identifier.citation | [1] R. Serrano et al., "A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications," 2021 18th International SoC Design Conference, Jeju Island, Republic of Korea, 2021, pp. 375-376.
[2] K. Nose and M. Mizuno, "Parallel clocking: a multi-phase clock-network for 10GHz SoC," 2004 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2004, pp. 344-531. [3] N. August, H.-J. Lee, M. Vandepas and R. Parker, "A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS," 2012 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2012, pp. 246-248. [4] H. Lakdawala et al., "32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver," 2012 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2012, pp. 62-64. [5] T.-H. Tsai, M.-S. Yuan, C.-H. Chang, C.-C. Liao, C.-C. Li and R. B. Staszewski, "A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CMOS," 2015 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2015, pp. 260-262. [6] L. Grimaldi et al., "A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS," 2019 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2019, pp. 268-270. [7] A. Santiccioli, M. Mercandelli, A. L. Lacaita, C. Samori and S. Levantino, "A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power," IEEE Journal of Solid-State Circuits, vol. 54, no. 11, pp. 3149-3160, Nov. 2019. [8] S. M. Dartizio et al., "A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering," IEEE Journal of Solid-State Circuits, vol. 58, no. 12, pp. 3320-3337, Dec. 2023. [9] Y. Zhao, M. Forghani and B. Razavi, "A 20-GHz PLL with 20.9-fs Random Jitter," IEEE Journal of Solid-State Circuits, vol. 58, no. 6, pp. 1597-1609, June 2023. [10] X. Geng, Y. Tian, Y. Xiao, Z. Ye, Q. Xie and Z. Wang, "A 25.8GHz Integer-N PLL with Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 388-390. [11] A. Elkholy, S. Saxena, G. Shu, A. Elshazly and P. K. Hanumolu, "Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers," IEEE Journal of Solid-State Circuits, vol. 53, no. 6, pp. 1806-1817, June 2018. [12] M. Zeinali, S.-Y. Hung and S. Pamarti, "Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation," IEEE Journal of Solid-State Circuits, vol. 59, no. 10, pp. 3417-3431, Oct. 2024. [13] Y. Yang et al., "A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration," 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 228-230. [14] C.-Y. Lin, W.-H. Chen, Y.-T. Hung, T.-J. Wang and T.-H. Lin, "An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration," IEEE Journal of Solid-State Circuits, vol. 59, no. 11, pp. 3705-3715, Nov. 2024. [15] T. A. D. Riley, M. A. Copeland and T. A. Kwasniewski, "Delta-sigma Modulation in Fractional-N Frequency Synthesis," IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May 1993. [16] S. Shin and H. -J. Yoo, "A Pipelined Time Stretching for High Throughput Counter-based Time-to-digital Converters," 2016 International SoC Design Conference (ISOCC), Jeju, Korea (South), 2016, pp. 57-58. [17] C. Li, L. Ma, J. Xiang and H. Min, "An Asynchronous Delay Line TDC for ADPLL in 0.13um CMOS," 2015 IEEE 11th International Conference on ASIC (ASICON), Chengdu, China, 2015, pp. 1-4. [18] P. Dudek, S. Szczepanski and J. V. Hatfield, "A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line," IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000. [19] P. Lu, Y. Wu and P. Andreani, "A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter with Digital Calibration," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 11, pp. 1019-1023, Nov. 2016. [20] M.-J. Yang, G. H. Kim and K.-Y. Lee, "A Small Area Cyclic Vernier Delay Line TDC Based ADDLL using Linear Delay Inverter," 2023 20th International SoC Design Conference (ISOCC), Jeju, Korea, Republic of, 2023, pp. 25-26. [21] M. Lee, M. E. Heidari and A. A. Abidi, "A Low Noise, Wideband Digital Phase-locked Loop based on a New Time-to-Digital Converter with Subpicosecond Resolution," 2008 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2008, pp. 112-113. [22] Jiren Yuan and C. Svensson, "New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings," IEEE Journal of Solid-State Circuits, vol. 32, no. 1, pp. 62-69, Jan. 1997. [23] F. Yuan, "Metastability Error Correction for True Single-Phase Clock DFF With Applications in Vernier TDC," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 11, pp. 4203-4207, Nov. 2022 [24] M. Lee and A. A. Abidi, "A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 769-777, April 2008. [25] A. Elkholy, T. Anand, W. -S. Choi, A. Elshazly and P. K. Hanumolu, "A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC," IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 867-881, April 2015. [26] L. Wang, G. Ye and Y. Huang, "A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS," 2021 IEEE 14th International Conference on ASIC (ASICON), Kunming, China, 2021, pp. 1-4. [27] E. Helal, E. Alvarez-Fontecilla, A. I. Eissa and I. Galton, "A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL," IEEE Journal of Solid-State Circuits, vol. 56, no. 9, pp. 2711-2723, Sept. 2021. [28] B. Kim, H. Kim and C. H. Kim, "An 8bit, 2.6ps Two-Step TDC in 65nm CMOS Employing a Switched Ring-Oscillator Based Time Amplifier," 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2015, pp. 1-4. [29] H. Chung, H. Ishikuro and T. Kuroda, "A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 47, no. 5, pp. 1232-1241, May 2012. [30] P. Kulkarni, S. Garg, S. Agrawal and M. S. Baghini, "Low Power Extended Range Multi-Modulus Divider Using True-Single-Phase-Clock Logic," 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), Guwahati, India, 2021, pp. 99-104. [31] M. Kreißig, M. El-Shennawy and F. Ellinger, "A Multi-Modulus Divider with High Sensitivity and Extended Division Range in 0.18 μm BiCMOS," 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), Monte Carlo, Monaco, 2016, pp. 213-216. [32] Q. J. Gu and Z. Gao, "A CMOS High Speed Multi-Modulus Divider with Retiming for Jitter Suppression," IEEE Microwave and Wireless Components Letters, vol. 23, no. 10, pp. 554-556, Oct. 2013. [33] A. Santiccioli, C. Samori, A. Lacaita, and S. Levantino, “Power-Jitter Trade-Off Analysis in Digital-to-Time Converters,” Electronics Letters, vol. 53, no. 5, pp. 306-308, Mar. 2017. [34] A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly and P. K. Hanumolu, "A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider," IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1771-1784, Aug. 2016. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96585 | - |
| dc.description.abstract | 本論文提出了一種具全數位背景校準功能的分數除頻器的設計與實現。一種新穎架構的不定時間數位轉換器被設計，實現低面積、高精確度的轉換，用於數位至時間轉換器的精確校準，且無需額外的類比電路。本作品基於不定時間數位轉換器的運作機制，開發了一套校準演算法於數位電路中執行，能夠在不中斷分數除頻操作的情況下實現背景校準。
本作品使用90奈米的CMOS製程製造，核心面積為0.021平方公釐，支援輸出頻率範圍為2.7兆赫至357兆赫，並採用21位元的分數編碼，使其輸出解析度可達25赫茲。量測結果顯示，在輸出頻率為269兆赫時，晶片整體功耗為4.23毫瓦，當背景校正完成後，分數突波可以從原先的-38.1dBc降低至-67.6dBc，整體抖動達到258飛秒。本作品提出的小數除頻器達到了-245.5dB的抖動量性能指標，展現出在分數除頻領域的領先性能表現。 | zh_TW |
| dc.description.abstract | In this thesis, we present the design and implementation of a fractional output divider (FOD) with all-digital background calibration. An indeterminate time-to-digital converter (ITDC) is designed to achieve high-resolution time-span digitization with minimal area overhead, achieving precise calibration of the digital-to-time converter (DTC) without additional analog circuits. Furthermore, a calibration algorithm is developed based on ITDC’s operation, which entirely conducts in digital domain, facilitating background calibration without interrupting the FOD's operation.
Fabricated in a 90nm CMOS process with a core area of 0.021 mm^2, the FOD supports an output frequency range from 2.7 MHz to 357 MHz with a resolution of 25 Hz with 21-bit fractional codes. Operating at an output frequency of 269 MHz, the power consumption is measured at 4.23 mW. Measurement results show a reduction in fractional spurs from -38.1 dBc to -67.6 dBc and an integrated jitter of 258 fs after calibration. The proposed FOD achieves a jitter figure-of-merit (FoM) of -245.5 dB, demonstrating its state-of-the-art performance in fractional output division. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-02-19T16:38:36Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-02-19T16:38:36Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 i
摘要 v Abstract vi Table of Contents vii List of Figures xi List of Tables xiv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 4 Chapter 2 Fundamentals of Fractional Output Dividers 5 2.1 Introduction to Fractional Output Dividers 5 2.1.1 Fractional Output Dividers with Delta-Sigma Modulation 5 2.1.2 Fractional Output Dividers with Digital-to-Time Converter Compensation 7 2.1.3 Challenges in DTC-based Fractional Output Divider 10 2.2 Replica-DTC-based Fractional Output Divider 12 2.2.1 Architecture of Replica-DTC-based Fractional Output Divider 13 2.2.2 Calibration Principle of the Replica-DTC-based Fractional Output Divider 14 2.2.3 Challenges in Replica-DTC-based Calibration 15 2.3 Phase-Rotating-based Fractional Output Divider 16 2.3.1 Calibration Principle of DTC Integral Non-Linearity 16 2.3.2 Architecture of Phase-Rotating-based Fractional Output Divider 18 2.3.3 Challenges in Phase-Rotating-based Calibration 19 2.4 PLL-assisted Fractional Output Divider 20 2.4.1 Architecture of PLL-assisted Fractional Output Divider 21 2.4.2 Challenges in PLL-assisted Calibration 23 2.5 Replica-DTC-free Fractional Output Divider 23 2.5.1 Architecture of Replica-DTC-Free Fractional Output Divider 24 2.5.2 Calibration Principle of Replica-DTC-Free Fractional Output Divider 25 2.5.3 Challenges in Replica-DTC-Free Calibration 25 2.6 Summary 26 Chapter 3 Architecture of the Proposed Indeterminate Time-to-Digital Converter 28 3.1 Introduction to Time-to-Digital Converters 28 3.1.1 Counter-based Time-to-Digital Converter 28 3.1.2 Delay Line Time-to-Digital Converter 29 3.1.3 Vernier Time-to-Digital Converter 30 3.2 Implementation of Indeterminate-Time-to-Digital Converter (ITDC) 31 3.2.1 Design Considerations 31 3.2.2 Specifications of Indeterminate Time-to-Digital Converter (ITDC) 32 3.2.3 Architecture of Indeterminate Time-to-Digital Converter (ITDC) 34 3.3 Operation of Indeterminate-Time-to-Digital Converter (ITDC) 36 3.3.1 Principles of Vernier TDC-based Signal Selection 36 3.3.2 Algorithm of ITDC Operation 37 3.4 Summary 40 Chapter 4 Proposed Fractional Output Divider with Indeterminate Time-to-Digital Converter-based Calibration 41 4.1 Principles of TDC-based DTC Background Calibration 41 4.1.1 Proposed TDC-based DTC gain calibration 41 4.1.2 Background Extraction of DTC’s Fully Adjustable Delay 42 4.1.3 Selection circuit for DTC background calibration 43 4.2 Proposed ITDC-based DTC Background Calibration 45 4.2.1 Indeterminate-TDC Operation in Two Modes 45 4.2.2 Complete Algorithm of ITDC for DTC Calibration 46 4.3 Full Architecture of the proposed ITDC-based FOD calibration 47 4.3.1 Proposed Fraction Output Divider Operation Mechanism 47 4.3.2 Specification of Dual-Divider Fraction Output Divider 49 4.3.3 Advantages of ITDC-based FOD Calibration 50 4.4 Circuit Implementation 51 4.4.1 Multi-Modulus Divider 51 4.4.2 Digital-to-Time Converter 52 4.4.3 Output Divider 53 4.5 System Simulation Results 54 4.5.1 DTC Characteristics 54 4.5.2 Peak-to-Peak Jitter through Eye Diagram 56 4.5.3 FOD’s Output Spectrum 56 4.5.4 Power Breakdown 57 4.6 Summary 58 Chapter 5 Measurement Results 59 5.1 Chip Micrograph 59 5.1.1 FOD Chip Layout 59 5.1.2 Chip Micrograph 60 5.2 Measurement Setup 61 5.3 Measurement Results 63 5.3.1 Measured Spectrum at Integer Mode 63 5.3.2 Measured Spectrum at Fractional Mode 64 5.3.3 Fractional Spur across Fractional Codes 66 5.3.4 Fractional Spur across DTC Gain (KDTC) Factors 66 5.3.5 Phase Noise and Calculated Integrated Jitter 67 5.3.6 Power Breakdown 69 5.4 Performance Summary 70 Chapter 6 Conclusions and Future Works 73 6.1 Conclusions 73 6.2 Future Works 74 References 75 | - |
| dc.language.iso | en | - |
| dc.title | 基於數位背景校正之小數除頻器設計 | zh_TW |
| dc.title | Design of a Fractional Output Divider with Digital Background Calibration | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 劉深淵;李泰成;陳筱青 | zh_TW |
| dc.contributor.oralexamcommittee | Shen-Iuan Liu;Tai-Cheng Lee;Hsiao-Chin Chen | en |
| dc.subject.keyword | 小數除頻器,數位時間轉換器,時間數位轉換器,時差放大器, | zh_TW |
| dc.subject.keyword | fractional output divider (FOD),digital-to-time converter (DTC),time-to-digital converter (TDC),time amplifier, | en |
| dc.relation.page | 79 | - |
| dc.identifier.doi | 10.6342/NTU202500089 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-01-14 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-113-1.pdf 目前未授權公開取用 | 6.06 MB | Adobe PDF |
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