從規格到佈局：基於人工智慧的類比電路自動化設計流程

Abstract

在本論文中，我們提出了一種基於人工智慧的設計和佈局自動化方法，並在28-nm CMOS技術中通過各種類型的類比電路進行驗證。此方法由三個步驟組成：1) 根據電路知識，透過 Cadence SKILL 程式碼中實現的參數化元件自動生成佈局資料集；2) 訓練佈局級神經網路(Neural Network, NN)模型以準確預測電路性能；3) 開發設計迭代迴圈來調整電路參數以達到設計目標。我們根據目標規格生成環形振盪器、兩級運算放大器和環形放大器的佈局，來證明這種方法的有效性。與人類設計從電路圖到佈局圖所需的時間相比，這種無需模擬的方法在環形振盪器、兩級運算放大器和環形放大器上，可以分別實現高達182倍、156倍，以及135倍的加速。

In this thesis, we present an AI-driven design and layout automation methodology validated with various types of analog circuits in a 28-nm CMOS technology. This approach is composed of three steps: 1) automatically generating a layout dataset by the parameterized cells implemented in a Cadence SKILL code based on the circuit knowledge, 2) training layout-level neural network (NN) model to predict circuit performance accurately, and 3) developing a design iteration loop to adjust circuit parameters and achieve the design target. We demonstrate the effectiveness of this methodology by generating layouts for a ring oscillator, a two-stage op amp, and a ring amplifier design based on their target specifications. Compared to the time required for a human to design from schematic to layout, our results indicate that this simulation-free methodology achieves speedups of up to 182, 156, and 135 times for ring oscillators, two-stage op amps, and ring amplifiers, respectively.