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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | zh_TW |
| dc.contributor.advisor | Tai-Cheng Lee | en |
| dc.contributor.author | 劉芳怡 | zh_TW |
| dc.contributor.author | Fang-Yi Liu | en |
| dc.date.accessioned | 2024-11-19T16:08:42Z | - |
| dc.date.available | 2024-11-20 | - |
| dc.date.copyright | 2024-11-19 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-11-11 | - |
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[2] T. Dhar, K. Kunal, Y. Li, M. Madhusudan, J. Poojary, A. K. Sharma, W. Xu, S. M. Burns, R. Harjani, J. Hu, D. A. Kirkpatrick, P. Mukherjee, S. Yaldiz, and S. S. Sapatnekar, “Align: A system for automating analog layout,” IEEE Design Test, vol. 38, pp. 8–18, Apr. 2021. [3] H. Chen, M. Liu, B. Xu, K. Zhu, X. Tang, S. Li, Y. Lin, N. Sun, and D. Z. Pan, “Magical: An open-source fully automated analog ic layout system from netlist to gdsii,” IEEE Design Test, vol. 38, pp. 19–26, Apr. 2021. [4] M.-J. Seo, Y.-J. Roh, D.-J. Chang, W. Kim, Y.-D. Kim, and S.-T. Ryu, “A reusable code-based sar adc design with cdac compiler and synthesizable analog building blocks,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 1904–1908, Dec. 2018. [5] Y.-H. Tsai and S.-I. Liu, “A 0.0067-mm2 12-bit 20-ms/s sar adc using digital place-and-route tools in 40nm cmos,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, pp. 905–914, July 2022. [6] P.-H. Wei and B. Murmann, “Analog and mixed-signal layout automation using digital place-and-route tools,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, pp. 1838–1849, Nov. 2021. [7] J. Liu, S. Su, M. Madhusudan, M. Hassanpourghadi, S. Saunders, Q. Zhang, R. Rasul, Y. Li, J. Hu, A. K. Sharma, S. S. Sapatnekar, R. Harjani, A. Levi, S. Gupta, and M. S.W. Chen, “From specification to silicon: Towards analog/mixed-signal design automation using surrogate nn models with transfer learning,” in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–9, Nov. 2021. [8] B. Razavi, Design of CMOS PhaseLocked Loops: From Circuit Level to Architecture Level. Cambridge University Press, 2020. [9] A. Homayoun and B. Razavi, “Relation between delay line phase noise and ring oscillator phase noise,” IEEE Journal of SolidState Circuits, vol. 49, pp. 384–391, Feb. 2014. [10] A. Sedra and K. Smith, Microelectronic Circuits 7th Edition, International Edition. Oxford University Press, 2015. [11] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.-K. Moon, “Ring amplifiers for switched capacitor circuits,” IEEE Journal of SolidState Circuits, vol. 47, pp. 2928–2942, Dec. 2012. [12] Y. Lim and M. P. Flynn, “A 100 ms/s, 10.5 bit, 2.46 mw comparatorless pipeline adc using self-biased ring amplifiers,” IEEE Journal of SolidState Circuits, vol. 50, pp. 2331–2341, Oct. 2015. [13] K. M. Megawer, F. A. Hussien, M. M. Aboudina, and A. N. Mohieldin, “A systematic design methodology for class-ab-style ring amplifiers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 1169–1173, Sep. 2018. [14] T. Barnes, “Skill: a cad system extension language,” in 27th ACM/IEEE Design Automation Conference, pp. 266–271, June 1990. [15] Cadence SKILL Language User Guide Product Version ICADVM18.1 October 2018. Cadence Design Systems, Inc., 2018. [16] Cadence SKILL Language Reference Product Version ICADVM18.1 October 2018. Cadence Design Systems, Inc., 2018. [17] Virtuoso Design Environment SKILL Reference Product Version ICADVM18.1 October 2018. Cadence Design Systems, Inc., 2018. [18] Virtuoso Parameterized Cell SKILL Reference Product Version ICADVM18.1 October 2018. Cadence Design Systems, Inc., 2018. [19] Virtuoso Relative Object Design User Guide Product Version ICADVM18.1 October 2018. Cadence Design Systems, Inc, 2018. [20] Virtuoso Relative Object Design SKILL Reference Product Version ICADVM18.1 October 2018. Cadence Design Systems, Inc., 2018. [21] OCEAN Reference Product Version ICADVM18.1 October 2018. Cadence Design Systems, Inc., 2018. [22] A. Jadon, A. Patil, and S. Jadon, “A comprehensive survey of regression based loss functions for time series forecasting,” arXiv preprint arXiv:2211.02989, 2022. [23] T. Tieleman, “Lecture 6.5-rmsprop: Divide the gradient by a running average of its recent magnitude,” 2012. [24] D. P. Kingma and J. Ba, “Adam: A method for stochastic optimization,” arXiv preprint arXiv:1412.6980, 2014. [25] F. Chollet, Deep Learning with Python, Second Edition. Manning, 2021. [26] J. Jalil, M. B. I. Reaz, and M. A. M. Ali, “Cmos differential ring oscillators: Review of the performance of cmos ros in communication systems,” IEEE Microwave Magazine, vol. 14, pp. 97–109, July 2013. [27] M. Mahendra, S. Kumari, M. Gupta, and A. Sangal, “Low voltage high performance super class ab ota design using sccm and dtmos with enhanced slew rate and dc gain,” Microelectronics Journal, vol. 113, p. 105101, 2021. [28] K. Hakhamaneshi, N. Werblun, P. Abbeel, and V. Stojanović, “Bagnet: Berkeley analog generator with layout optimizer boosted with deep neural networks,” in 2019 IEEE/ACM International Conference on ComputerAided Design (ICCAD), pp. 1–8, Nov. 2019. [29] S. S. Sapatnekar, “Automating analog layout: Why this time is different,” in IEEE CASS RS Talks, May 2021. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96170 | - |
| dc.description.abstract | 在本論文中，我們提出了一種基於人工智慧的設計和佈局自動化方法，並在28-nm CMOS技術中通過各種類型的類比電路進行驗證。此方法由三個步驟組成：1) 根據電路知識，透過 Cadence SKILL 程式碼中實現的參數化元件自動生成佈局資料集；2) 訓練佈局級神經網路(Neural Network, NN)模型以準確預測電路性能；3) 開發設計迭代迴圈來調整電路參數以達到設計目標。我們根據目標規格生成環形振盪器、兩級運算放大器和環形放大器的佈局，來證明這種方法的有效性。與人類設計從電路圖到佈局圖所需的時間相比，這種無需模擬的方法在環形振盪器、兩級運算放大器和環形放大器上，可以分別實現高達182倍、156倍，以及135倍的加速。 | zh_TW |
| dc.description.abstract | In this thesis, we present an AI-driven design and layout automation methodology validated with various types of analog circuits in a 28-nm CMOS technology. This approach is composed of three steps: 1) automatically generating a layout dataset by the parameterized cells implemented in a Cadence SKILL code based on the circuit knowledge, 2) training layout-level neural network (NN) model to predict circuit performance accurately, and 3) developing a design iteration loop to adjust circuit parameters and achieve the design target. We demonstrate the effectiveness of this methodology by generating layouts for a ring oscillator, a two-stage op amp, and a ring amplifier design based on their target specifications. Compared to the time required for a human to design from schematic to layout, our results indicate that this simulation-free methodology achieves speedups of up to 182, 156, and 135 times for ring oscillators, two-stage op amps, and ring amplifiers, respectively. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-11-19T16:08:42Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-11-19T16:08:42Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 iii
摘要 v Abstract vi Contents vii List of Figures x List of Tables xii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Prior Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Fundamentals 4 2.1 Introduction of ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.1 Oscillation frequency . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.2 Phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.3 Figure of merit (FoM) . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Introduction of twostage op amp . . . . . . . . . . . . . . . . . . . . . . 5 2.2.1 DC gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.2 Frequency response and compensation . . . . . . . . . . . . . . . 7 2.3 Introduction of ring amplifier . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.1 Slewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2 Stabilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.3 Steady state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 Introduction of Cadence SKILL . . . . . . . . . . . . . . . . . . . . . . 12 2.4.1 Relative Object Design (ROD) . . . . . . . . . . . . . . . . . . . 13 2.4.2 Open Command Environment for Analysis (OCEAN) . . . . . . 13 2.5 Introduction of machine learning (ML) . . . . . . . . . . . . . . . . . . . 14 2.5.1 Supervised learning . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.2 Unsupervised learning . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.3 Reinforcement learning . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.4 Workflow of machine learning . . . . . . . . . . . . . . . . . . . 16 2.5.5 Overfitting and underfitting . . . . . . . . . . . . . . . . . . . . 16 2.5.6 Training, validation and testing dataset . . . . . . . . . . . . . . 17 2.6 Introduction of Neural Network (NN) . . . . . . . . . . . . . . . . . . . 18 2.6.1 Architecture of NN . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6.2 Training process of NN . . . . . . . . . . . . . . . . . . . . . . . 18 2.6.3 Loss function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.6.4 Optimizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 Proposed Design Automation Flow 23 3.1 Dataset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.1 Ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2 Twostage op amp . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3 Ring amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2 NN model training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.1 Ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.2 Twostage op amp . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.3 Ring amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3 Design iteration loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4 Results 49 4.1 Dataset generation and NN model training . . . . . . . . . . . . . . . . . 49 4.2 Design iteration loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5 Conclusion 55 5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Bibliography 57 | - |
| dc.language.iso | en | - |
| dc.subject | 神經網路 | zh_TW |
| dc.subject | 類比設計自動化 | zh_TW |
| dc.subject | 佈局自動化 | zh_TW |
| dc.subject | Neural network | en |
| dc.subject | Layout automation | en |
| dc.subject | Analog design automation | en |
| dc.title | 從規格到佈局：基於人工智慧的類比電路自動化設計流程 | zh_TW |
| dc.title | From Specification to Layout: An AI-driven Automation Design Flow for Analog Circuits | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 劉深淵;劉宗德;范育成 | zh_TW |
| dc.contributor.oralexamcommittee | Shen-Iuan Liu;Tsung-Te Liu;Yu-Cheng Fan | en |
| dc.subject.keyword | 類比設計自動化,佈局自動化,神經網路, | zh_TW |
| dc.subject.keyword | Analog design automation,Layout automation,Neural network, | en |
| dc.relation.page | 60 | - |
| dc.identifier.doi | 10.6342/NTU202404549 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-11-11 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 積體電路設計與自動化學位學程 | - |
| 顯示於系所單位： | 積體電路設計與自動化學位學程 | |
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