具電流控制震盪器相位比較陣列量化器之二階連續時間三角積分器

Abstract

隨著物聯網蓬勃發展，不僅促進了人們生活上的便利性，也讓相關系統的需求隨之上升。其中感測器做為物聯網中偵測外界訊號的介面，必須具備能準確接受外界訊號並輸入系統的能力。在生醫相關的應用中，待測訊號多半具有低頻、低振幅的特性，故在感測器的設計上需滿足在低頻段中有著高解析度的特性，同時為降低成本、提升產品使用壽命，低功耗和較小的面積也是設計目標之一。 本論文實作了一個二階連續時間三角積分類比數位轉換器，製造於台積電180奈米製程。為了降低功耗以及因應未來的製程演進，選擇使用兩級共四顆環形震盪器取代了過往常見的類比積分器，並透過差動路徑間相位的比較讀取出數位輸出。受益於二階三角積分調變，在低頻時量化雜訊較低，進而提升信噪比。量化器採用多個相位頻率偵測器，輸入僅需第二級的環形震盪器的各相位輸出，無須額外的參考電壓或校正系統。 此晶片供應電壓為1.2伏特，功耗為33.26μW，核心面積為0.74mm2，輸入範圍至多為500nApp，頻寬為3kHz，在模擬上達到了73.16dB的信噪比，品質因素達到FoMs = 153.22dB以及FoMw = 1.32pJ/conv。

With the rapid development of the Internet of Things (IoT), there is increased demand for systems that enhance convenience and functionality. Sensors, crucial for detecting external signals in IoT, must accurately capture and input these signals. In biomedical applications, signals typically have low frequency and amplitude, requiring sensors to have high resolution in the low-frequency range. Additionally, low power consumption and compact size are important to reduce costs and extend product lifespan. This thesis presents a second-order continuous-time delta-sigma modulator implemented in TSMC’s 180nm process. To minimize power consumption and accommodate future process advancements, the design replaces traditional analog integrators with a two-stage architecture using four ring oscillators. Digital outputs are generated by comparing phases between differential paths. The second-order delta-sigma modulation improves the signal-to-noise ratio (SNR) by reducing quantization noise at low frequencies. The quantizer utilizes multiple phase frequency detectors, requiring only the phase outputs from the second-stage ring oscillators without additional reference voltages or calibration. The chip operates at 1.2V with a power consumption of 33.26μW and a core area of 0.74mm². It supports a maximum input range of 500nApp and a bandwidth of 3kHz. Simulations show an SNR of 73.16dB, a figure of merit (FoM) of 153.22dB, and a figure of merit per watt (FoMw) of 1.32pJ/conv.