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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | zh_TW |
| dc.contributor.advisor | Tsung-Hsien Lin | en |
| dc.contributor.author | 楊政道 | zh_TW |
| dc.contributor.author | Cheng-Tao Yang | en |
| dc.date.accessioned | 2024-10-14T16:10:17Z | - |
| dc.date.available | 2024-10-15 | - |
| dc.date.copyright | 2024-10-14 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-09-24 | - |
| dc.identifier.citation | [1] J. F. Witte, K. A. A. Makinwa, and J. H. Huijsing, “Dynamic Offset Compensated CMOS Amplifiers”, Springer, 2009.
[2] Q. Fan, K. A. A. Makinwa, and J. H. Huijsing, ”Capacitively-Coupled Chopper Amplifiers”, Springer, 2017. [3] R. F. Yazicioglu, S. Kim, T. Torfs, H. Kim, and C. V. Hoof, “A 30 μW analog signal processor ASIC for portable biopotential signal monitoring,” IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 209–223, Jan. 2011 [4] C. Lee et al., “A 6.5μW 10skHz-BW 80.4dB-SNDR Continuous-Time Δ∑ Modulator with Gm-Input and 300 mVpp Linear Input Range for Closed-Loop Neural Recording,” ISSCC, pp. 410-411, Feb. 2020. [5] J. Huang et al., “A -105dB THD 88dB-SNDR VCO-based Sensor Front-end Enabled by Background Calibrated Differential Pulse Code Modulation,” IEEE Symp. VLSI Circuits, June 2020. [6] S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta-Sigma Data Converters. New York, Hoboken, New Jersey: IEEE Press ; Wiley, 2017. [7] J. Huang and P. P. Mercier, “A 178.9-DB FOM 128-DB SFDR VCO-based AFE for ExG readouts with a calibration-free differential pulse code modulation technique,” IEEE Journal of Solid-State Circuits, vol. 56, no. 11, pp. 3236–3246, Nov. 2021. [8] G. Taylor and I. Galton, “A mostly-digital variable-rate continuous-time delta-sigma modulator ADC,” IEEE J. Solid-State Circuits, vol 45, pp. 2634-2646, Dec. 2010. [9] C. C. Tu, Y. K. Wang, and T. H. Lin, "A Low-Noise Area-Efficient Chopped VCO-Based CTDSM for Sensor Applications in 40-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2523-2532, Oct. 2017. [10] M. Z. Straayer and M. H. Perrott, “A 12-Bit, 10-MHz bandwidth, continuous-time ΣΔ ADC with a 5-Bit, 950-MS/s VCO-based quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, Apr. 2008. [11] C. C. Tu, Y. K. Wang, and T. H. Lin, "A 0.06 mm2 ± 50 mV Range −82dB THD Chopper VCO-Based Sensor Readout Circuit in 40nm CMOS," 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C84-C85. [12] K. Lee, Y. Yoon, and N. Sun, “A scaling-friendly low-power small-area ADC with VCO-based integrator and intrinsic mismatch shaping capability,” IEEE Trans. Emerg. Sel. Topics Circuits Syst., vol. 5, no. 4, pp. 561–573, Dec. 2015. [13] M. Z. Straayer and M. H. Perrott, “A 12-Bit, 10-MHz bandwidth, continuous-time Δ∑ ADC with a 5-bit, 950-MS/s VCO-based quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, Apr. 2008. [14] A. Babaie-Fishani and P. Rombouts, “A mostly digital VCO-based CT SDM with third-order noise shaping,” IEEE J. Solid-State Circuits, vol. 52, no. 8, pp. 2141–2153, Aug. 2017. [15] M. Baert and W. Dehaene, “A 5-GS/s 7.2-ENOB time-interleaved VCO-based ADC achieving 30.5 FJ/CS,” IEEE Journal of Solid-State Circuits, pp. 1–11, 2020. [16] Collin Wells, "High-Side Voltage-to-Current (V-I) Converter," TI Precision Designs: Verified Design, 2013. [17] W. Jiang, V. Hokhikyan, H. Chandrakumar, V. Karkare, and D. Markovic, "A ± 50mV Linear-Input-Range VCO-based Neural-Recording Front-End with Digital Nonlinearity Correction," IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 173-184, Jan. 2017 [18] Jayaraj, M. Danesh, S. T. Chandrasekaran and A. Sanyal, "Highly Digital Second-Order ΔΣ VCO ADC," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. 2415-2425, July 2019. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96094 | - |
| dc.description.abstract | 隨著物聯網蓬勃發展，不僅促進了人們生活上的便利性，也讓相關系統的需求隨之上升。其中感測器做為物聯網中偵測外界訊號的介面，必須具備能準確接受外界訊號並輸入系統的能力。在生醫相關的應用中，待測訊號多半具有低頻、低振幅的特性，故在感測器的設計上需滿足在低頻段中有著高解析度的特性，同時為降低成本、提升產品使用壽命，低功耗和較小的面積也是設計目標之一。
本論文實作了一個二階連續時間三角積分類比數位轉換器，製造於台積電180奈米製程。為了降低功耗以及因應未來的製程演進，選擇使用兩級共四顆環形震盪器取代了過往常見的類比積分器，並透過差動路徑間相位的比較讀取出數位輸出。受益於二階三角積分調變，在低頻時量化雜訊較低，進而提升信噪比。量化器採用多個相位頻率偵測器，輸入僅需第二級的環形震盪器的各相位輸出，無須額外的參考電壓或校正系統。 此晶片供應電壓為1.2伏特，功耗為33.26μW，核心面積為0.74mm2，輸入範圍至多為500nApp，頻寬為3kHz，在模擬上達到了73.16dB的信噪比，品質因素達到FoMs = 153.22dB以及FoMw = 1.32pJ/conv。 | zh_TW |
| dc.description.abstract | With the rapid development of the Internet of Things (IoT), there is increased demand for systems that enhance convenience and functionality. Sensors, crucial for detecting external signals in IoT, must accurately capture and input these signals. In biomedical applications, signals typically have low frequency and amplitude, requiring sensors to have high resolution in the low-frequency range. Additionally, low power consumption and compact size are important to reduce costs and extend product lifespan.
This thesis presents a second-order continuous-time delta-sigma modulator implemented in TSMC’s 180nm process. To minimize power consumption and accommodate future process advancements, the design replaces traditional analog integrators with a two-stage architecture using four ring oscillators. Digital outputs are generated by comparing phases between differential paths. The second-order delta-sigma modulation improves the signal-to-noise ratio (SNR) by reducing quantization noise at low frequencies. The quantizer utilizes multiple phase frequency detectors, requiring only the phase outputs from the second-stage ring oscillators without additional reference voltages or calibration. The chip operates at 1.2V with a power consumption of 33.26μW and a core area of 0.74mm². It supports a maximum input range of 500nApp and a bandwidth of 3kHz. Simulations show an SNR of 73.16dB, a figure of merit (FoM) of 153.22dB, and a figure of merit per watt (FoMw) of 1.32pJ/conv. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-10-14T16:10:17Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-10-14T16:10:17Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 論文口試委員審定書 iii
摘要 i Abstract iii List of Figures vii List of Tables x Chapter 1 Introduction 1 1.1 Background 1 1.2 Dissertation Overview 2 Chapter 2 Fundamental of Sensor Interface Circuit and Prior Art 3 2.1 Basic Sensor Read-Out Systems 3 2.2 Delta-Sigma Modulators 6 2.2.1 Introduction of Oversampling 6 2.2.2 Introduction of Delta-Sigma Modulator 8 2.2.3 VCO-based Delta-Sigma Modulator ADC 13 2.2.4 VCO-based Quantizer 16 Chapter 3 Design of a 2nd-order CCO-based CTDSM with PFD Array Quantizer 21 3.1 Introduction 21 3.1.1 Single-phase scenario 23 3.1.2 Multi-phase scenario 27 3.1.3 Steady-state operation 31 3.2 System Architecture 32 3.3 Circuit Implementation 40 3.3.1 First Stage and Second Stage Current-Controlled Oscillator(CCO) 40 3.3.2 Phase Frequency Detector(PFD) 44 3.3.3 Current-Controlled Circuit and Current DAC 48 3.3.4 Thermometer-to-Binary Converter(T2B) 52 3.4 Noise Calculation 53 3.5 Simulation 56 Chapter 4 Experimental Result of the Proposed 2nd -order CTDSM with PFD Array Quantizer 58 4.1 Die Photo 58 4.2 Measurement Setup 59 4.3 Measurement Result 60 4.3.1 Power Breakdown 60 4.3.2 CCO Measurement 61 4.3.3 Comparison Table 67 4.3.4 Discussion and Summary 68 Chapter 5 Conclusions and Future Works 69 5.1 Conclusions 69 5.2 Future Works 70 References 72 | - |
| dc.language.iso | en | - |
| dc.title | 具電流控制震盪器相位比較陣列量化器之二階連續時間三角積分器 | zh_TW |
| dc.title | Design of a 2nd-order Continuous-Time Delta-Sigma ADC with a CCO-Based PFD Array Quantizer | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳信樹;陳筱青 | zh_TW |
| dc.contributor.oralexamcommittee | Hsin-Shu Chen;Hsiao-Chin Chen | en |
| dc.subject.keyword | 低功耗,類比數位轉換器,三角積分器,感測電路,電流控制震盪器,多相位頻率偵測器, | zh_TW |
| dc.subject.keyword | Low-Power,Analog-to-Digital Converter (ADC),Delta-Sigma Modulator (DSM),Sensor,Current-Controlled Oscillator (CCO),Multi-PFD Detector, | en |
| dc.relation.page | 74 | - |
| dc.identifier.doi | 10.6342/NTU202404399 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2024-09-24 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2029-09-22 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-113-1.pdf 未授權公開取用 | 2.85 MB | Adobe PDF | 檢視/開啟 |
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