與後段製程兼容之P型氧化物半導體薄膜電晶體製程開發與可靠度檢測

Abstract

本論文主要開發適合應用於單體三維結構中，堆疊於上層之氧化亞銅薄膜電晶體，並藉由濺鍍薄膜與隨後的沉積後退火，合成出適合應用於薄膜電晶體通道材料的氧化亞銅薄膜，在探討氧化亞銅材料氧化還原的過程中，建立了一套在低溫下可以製作出高品質氧化亞銅的方式，並將它應用在薄膜電晶體之中，透過在300°C下使用直流濺鍍技術製備12奈米厚的純銅並進行熱氧化，成功合成了適用於薄膜電晶體的高品質氧化亞銅薄膜。這種高溫濺鍍過程有助於減少銅間隙對少數載子（電子）的累積，從而降低漏電流。此外，為了進一步降低電晶體的關電流，利用PEALD技術在電晶體表面鍍上10奈米的Al2O3作為鈍化層。經過電性分析和穿透式電子顯微鏡的驗證，Al2O3層通過場效應鈍化和化學鈍化有效降低了氧化亞銅表面的電子電洞復合率和缺陷數量，缺陷密度顯著降低至7.52×1012 eV-1cm-2，實現了極低的關電流（10-13 A）和高開關電流比（1.36×106）。這證明了濺鍍純金屬結合適當的熱氧化和鈍化處理，可以製備出具有優良開關特性的電晶體。 為了確保製造的氧化亞銅薄膜電晶體具備高度穩定性，本研究透過正偏壓應力（PBS）和負偏壓應力（NBS）的可靠性測試。在NBS測試中，閾值電壓的顯著變動遵循拉伸指數函數，表明主要的不穩定因素為通道材料與介電質界面處的電洞捕捉。而PBS測試中閾值電壓的輕微變化則證實了鈍化層與通道材料之間缺陷捕捉的現象極少，這增強了裝置的穩定性並有助於延長其使用壽命。

This thesis focuses on developing copper oxide (Cu₂O) thin-film transistors suitable for monolithic 3D structures. Utilizing DC sputtering at 300°C to deposit 12 nm of pure copper followed by thermal oxidation, we synthesized high-quality Cu₂O films ideal for TFT channel materials. The higher sputtering temperature effectively reduces minority carrier (electron) accumulation, thus lowering leakage current. Furthermore, to decrease the transistor's off-current, a 10 nm layer of Al2O3 was deposited using PEALD as a passivation layer. Electrical analysis and TEM verification showed that the Al2O3 layer reduces electron-hole recombination and defect density on the Cu₂O surface, significantly lowering defect density to 7.52×10¹² eV⁻¹cm⁻² and achieving an extremely low off-current (10⁻¹³ A) with a high on/off current ratio (1.36×10⁶). This demonstrates that sputtering pure metals, combined with appropriate thermal oxidation and passivation, can fabricate transistors with excellent switching characteristics. Reliability tests, PBS, and NBS, confirm the high stability of the fabricated Cu₂O TFTs. NBS tests show significant Vt shifts following a stretch-exponential function, indicating instability primarily due to hole trapping at the channel material-dielectric interface. In contrast, minimal Vt shift in PBS tests confirms few defect captures between the passivation layer and channel material, enhancing device stability and lifespan. Reliability tests, PBS, and NBS, confirm the high stability of the fabricated Cu₂O TFTs. NBS tests show significant Vt shifts following a stretch-exponential function, indicating instability primarily due to hole trapping at the channel material-dielectric interface. In contrast, minimal Vt shift in PBS tests confirms few defect captures between the passivation layer and channel material, enhancing device stability and lifespan.