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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳志毅 | zh_TW |
| dc.contributor.advisor | Chih-I Wu | en |
| dc.contributor.author | 駱宗典 | zh_TW |
| dc.contributor.author | Tsung-Tien Lo | en |
| dc.date.accessioned | 2024-09-18T16:21:20Z | - |
| dc.date.available | 2024-09-19 | - |
| dc.date.copyright | 2024-09-18 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-10 | - |
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Ho, "Revisiting MOSFET threshold voltage extraction methods," Microelectronics Reliability, vol. 53, no. 1, pp. 90-104, 2013. [21] A. Es-Sakhi and M. H. Chowdhury, "Analytical model to estimate the subthreshold swing of SOI FinFET," in 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 2013: IEEE, pp. 52-55. [22] W.-Y. Yang and S.-W. Rhee, "Effect of electrode material on the resistance switching of Cu2O film," Applied Physics Letters, vol. 91, no. 23, 2007. [23] C. Wang et al., "Enhanced performances of a-IGZO TFTs with oxide passivation layers fabricated by hollow cathode assisted PLD," Journal of Alloys and Compounds, vol. 961, p. 170972, 2023. [24] E. Fortunato et al., "Thin-film transistors based on p-type Cu2O thin films produced at room temperature," Applied Physics Letters, vol. 96, no. 19, 2010. [25] S.-Y. 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Jeong et al., "Origin of subthreshold swing improvement in amorphous indium gallium zinc oxide transistors," Electrochemical and Solid-State Letters, vol. 11, no. 6, p. H157, 2008. [39] H. Kawazoe, M. Yasukawa, H. Hyodo, M. Kurita, H. Yanagi, and H. Hosono, "P-type electrical conduction in transparent thin films of CuAlO2," Nature, vol. 389, no. 6654, pp. 939-942, 1997. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/95849 | - |
| dc.description.abstract | 本論文主要開發適合應用於單體三維結構中，堆疊於上層之氧化亞銅薄膜電晶體，並藉由濺鍍薄膜與隨後的沉積後退火，合成出適合應用於薄膜電晶體通道材料的氧化亞銅薄膜，在探討氧化亞銅材料氧化還原的過程中，建立了一套在低溫下可以製作出高品質氧化亞銅的方式，並將它應用在薄膜電晶體之中，透過在300°C下使用直流濺鍍技術製備12奈米厚的純銅並進行熱氧化，成功合成了適用於薄膜電晶體的高品質氧化亞銅薄膜。這種高溫濺鍍過程有助於減少銅間隙對少數載子（電子）的累積，從而降低漏電流。此外，為了進一步降低電晶體的關電流，利用PEALD技術在電晶體表面鍍上10奈米的Al2O3作為鈍化層。經過電性分析和穿透式電子顯微鏡的驗證，Al2O3層通過場效應鈍化和化學鈍化有效降低了氧化亞銅表面的電子電洞復合率和缺陷數量，缺陷密度顯著降低至7.52×1012 eV-1cm-2，實現了極低的關電流（10-13 A）和高開關電流比（1.36×106）。這證明了濺鍍純金屬結合適當的熱氧化和鈍化處理，可以製備出具有優良開關特性的電晶體。
為了確保製造的氧化亞銅薄膜電晶體具備高度穩定性，本研究透過正偏壓應力（PBS）和負偏壓應力（NBS）的可靠性測試。在NBS測試中，閾值電壓的顯著變動遵循拉伸指數函數，表明主要的不穩定因素為通道材料與介電質界面處的電洞捕捉。而PBS測試中閾值電壓的輕微變化則證實了鈍化層與通道材料之間缺陷捕捉的現象極少，這增強了裝置的穩定性並有助於延長其使用壽命。 | zh_TW |
| dc.description.abstract | This thesis focuses on developing copper oxide (Cu₂O) thin-film transistors suitable for monolithic 3D structures. Utilizing DC sputtering at 300°C to deposit 12 nm of pure copper followed by thermal oxidation, we synthesized high-quality Cu₂O films ideal for TFT channel materials. The higher sputtering temperature effectively reduces minority carrier (electron) accumulation, thus lowering leakage current. Furthermore, to decrease the transistor's off-current, a 10 nm layer of Al2O3 was deposited using PEALD as a passivation layer. Electrical analysis and TEM verification showed that the Al2O3 layer reduces electron-hole recombination and defect density on the Cu₂O surface, significantly lowering defect density to 7.52×10¹² eV⁻¹cm⁻² and achieving an extremely low off-current (10⁻¹³ A) with a high on/off current ratio (1.36×10⁶). This demonstrates that sputtering pure metals, combined with appropriate thermal oxidation and passivation, can fabricate transistors with excellent switching characteristics.
Reliability tests, PBS, and NBS, confirm the high stability of the fabricated Cu₂O TFTs. NBS tests show significant Vt shifts following a stretch-exponential function, indicating instability primarily due to hole trapping at the channel material-dielectric interface. In contrast, minimal Vt shift in PBS tests confirms few defect captures between the passivation layer and channel material, enhancing device stability and lifespan. Reliability tests, PBS, and NBS, confirm the high stability of the fabricated Cu₂O TFTs. NBS tests show significant Vt shifts following a stretch-exponential function, indicating instability primarily due to hole trapping at the channel material-dielectric interface. In contrast, minimal Vt shift in PBS tests confirms few defect captures between the passivation layer and channel material, enhancing device stability and lifespan. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-09-18T16:21:20Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-09-18T16:21:20Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 I
摘要 III ABSTRACT IV 目次 V 圖次 VIII 表次 XII 第一章 緒論 1 1.1 半導體的發展概述 1 1.1.1 摩爾定律 1 1.1.2 製程演進 2 1.1.3 單體三維的發展性 4 1.2 金屬氧化物半導體介紹 7 1.2.1 金屬氧化物半導體的應用 7 1.2.2 金屬氧化物半導體的瓶頸 9 1.2.3 P型金屬氧化物半導體 11 1.3 氧化亞銅簡介 12 1.3.1 二元氧化銅的簡介 12 1.3.2 氧化亞銅的結構及特性 14 1.3.3 氧化亞銅的製備方式 15 1.4 研究動機 16 第二章 實驗理論與方法 18 2.1 製程設備簡介 18 2.1.1 磁控式濺鍍系統(magnetron Sputtering) 18 2.1.2 快速熱退火(Rapid thermal Annealing) 20 2.1.3 步進式曝光機(Stepper Aligner) 21 2.1.4 電子束金屬蒸鍍機(E-gun metal Evaporator) 22 2.1.5 原子層沉積 (Atomic Layer Deposition) 24 2.1.6 超臨界流體系統(Supercritical fluids) 26 2.2 量測儀器簡介 27 2.2.1 光致發光與拉曼光譜分析儀(Raman Spectroscopy) 27 2.2.2 掃描式電子顯微鏡(Scanning Electron Microscope, SEM) 29 2.2.3 穿透式電子顯微鏡(Transmission Electron Microscope) 30 2.2.4 X光繞射儀(X-ray Diffraction, XRD) 31 2.2.5 X射線光電子能譜(X-ray photoelectron spectroscopy, XPS) 33 2.2.6 元件電性量測系統 34 2.3 薄膜電晶體元件參數 35 2.3.1 傳輸曲線 35 2.3.2 開關電流比 36 2.3.3 臨界電壓 36 2.3.4 場效遷移率 38 2.3.5 次臨界擺幅 39 2.4 氧化亞銅電晶體的製備方式 39 2.4.1 濺鍍通道材料 40 2.4.2 沉積後退火 41 2.4.3 曝光與蒸鍍金屬電極 41 2.4.4 曝光與蝕刻溝槽 42 2.4.5 原子層沉積氧化鋁鈍化層 43 2.4.6 超臨界流體 44 第三章 材料分析 45 3.1 氧化亞銅的材料分析 45 3.1.1 濺鍍分壓對於氧化亞銅薄膜之分析 45 3.1.2 沉積後退火對於氧化亞銅薄膜之分析 51 3.1.3 沉積厚度對於氧化亞銅薄膜之分析 55 3.2 氧化亞銅薄膜電晶體 57 3.2.1 氧化亞銅薄膜電晶體的製作流程 58 3.2.2 通道厚度對於電晶體的影響 58 3.2.3 掀離製程與蝕刻製程對電晶體的影響 62 3.2.4 鈍化層與升溫濺鍍對於電晶體關電流的影響 63 3.2.5 成膜性值對於電性的影響 67 第四章 可靠度分析 73 4.1 鈍化層與氧化亞銅界面分析 73 4.2 ALD與PEALD 76 4.3 可靠度量測 79 第五章 結論 83 參考文獻 85 | - |
| dc.language.iso | zh_TW | - |
| dc.title | 與後段製程兼容之P型氧化物半導體薄膜電晶體製程開發與可靠度檢測 | zh_TW |
| dc.title | P-type Oxide Semiconductor Thin Film Transistors with Back-End-of-Line Compatible Process and Reliability Testing | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳美杏;吳肇欣;陳奕君;張子璿 | zh_TW |
| dc.contributor.oralexamcommittee | Mei-Hsin Chen;Chao-Hsin Wu;I-Chun Cheng;Tzu-Hsuan Chang | en |
| dc.subject.keyword | 氧化亞銅,與後端製程相容,低熱運算,低漏電流,高穩定性,直流濺鍍,沉積後退火, | zh_TW |
| dc.subject.keyword | Copper Oxide,BEOL compatibility,low thermal budget,low leakage current,high stability,DC sputtering,post-deposition annealing, | en |
| dc.relation.page | 89 | - |
| dc.identifier.doi | 10.6342/NTU202403078 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2024-08-13 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 光電工程學研究所 | - |
| dc.date.embargo-lift | 2029-08-01 | - |
| 顯示於系所單位： | 光電工程學研究所 | |
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