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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎 | zh_TW |
| dc.contributor.advisor | Jiun-Lang Huang | en |
| dc.contributor.author | 顏伯任 | zh_TW |
| dc.contributor.author | Po-Jen Yen | en |
| dc.date.accessioned | 2024-09-16T16:19:19Z | - |
| dc.date.available | 2024-09-17 | - |
| dc.date.copyright | 2024-09-16 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-07-31 | - |
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[28] J.C.Lee,J.Kim,K.W.Kim,Y.J.Ku,D.S.Kim,C.Jeong,T.S.Yun,H.Kim,H.S. Cho, S. Oh, H. S. Lee, K. H. Kwon, D. B. Lee, Y. J. Choi, J. Lee, H. G. Kim, J. H.Chun, J. Oh, and S. H. Lee, “High bandwidth memory(HBM) with TSV technique,” in 2016 International SoC Design Conference (ISOCC), pp. 181–182, 2016. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/95765 | - |
| dc.description.abstract | 3D-IC技術在現今IC設計中已成為AI晶片發展的關鍵。通過堆疊小晶片並使用互連作為資料傳輸的媒介，可以增加資料傳輸速度、減少傳輸距離和能耗。然而，由於互連的高密度放，晶片在製造過程中容易產生缺陷 (defects)，因此互連的測試和可靠性是一個重要議題。
不同種類的缺陷，如短路、開路和串擾故障，都需要有對應的測試模型來進行檢驗。由於在 3D-IC中高密度的互連使得串擾效應增大，串擾故障的風險顯著提升。因此串擾故障模型 (Crosstalk Fault Model) 的討論逐漸成為當前的探討的重點。 本篇提出了一種測試以及修復分析方案，能夠高效地進行串擾測試以及修復。我們提出了一種可重複使用的測試元件，在正常運作模式下可作為修復訊號的儲存空間。這種設計大幅降低測試和修復成本，顯著提升系統的可靠性並降低製造成本。 | zh_TW |
| dc.description.abstract | 3D-IC technology has become crucial in modern IC design for the development of AI chips. By stacking small chiplets and using interconnects as data transmission media, data transfer speed can be increased, while transmission distance and power consumption are also reduced. However, due to the high-density placement of interconnects, defects can easily occur during the chip manufacturing process. Therefore, testing and reliability of interconnects are crucial issues.
Different types of defects, such as shorts, opens, and crosstalk faults, all require cor- responding test models for validation. Due to the high-density interconnects in 3D-ICs, crosstalk effects are amplified, significantly increasing the risk of crosstalk faults. There- fore, discussions on the Crosstalk Fault Model have gradually become a focal point of current research. This paper proposes a testing and repair analysis scheme that can efficiently perform crosstalk testing and repair. We propose a reusable testing component that can serve as storage for repair signals during normal operation mode. This design significantly reduces testing and repair costs, enhances system reliability, and lowers manufacturing expenses. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-09-16T16:19:19Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-09-16T16:19:19Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements ........................ i
摘要 ........................ ii Abstract ........................ iii Chapter1 Introduction ........................ 1 1.1 Overview of 2.5D/3D-IC ........................ 1 1.2 Importance of Interconnect Testing .................. 2 1.3 Related work .............................. 3 1.4 Motivation ............................... 6 1.5 Contribution .............................. 7 1.6 Organization of the Thesis ....................... 8 Chapter2 Preliminaries ........................ 9 2.1 Maximum Aggressor Fault(MAF)Model ....................... 9 2.2 Kth Aggressor Fault(KAF)Model ................... 10 2.3 Interconnect Testing with IEEE1500 Standard ................... 11 2.3.1 IEEE1500 WBR for Single Pattern Application ................... 11 2.3.2 IEEE1500 Test Architecture ..................... 12 2.3.3 IEEE1500 WBR for Two Pattern Application ................... 13 2.4 IEEE 1500 Based TSV Array Crosstalk Test Solution ................... 14 2.4.1 Modified WBR cell based on IEEE1500 ........................ 14 2.4.2 Flip Signal Generation Mechanism .................. 15 2.4.3 Crosstalk Test Scheme ........................ 16 2.5 Interconnect Labeling Method ..................... 17 2.6 General Repair Mechanism ....................... 18 Chapter3 Proposed Method ....................... 19 3.1 Proposed DfT Architecture and Test Scheme ...................... 19 3.1.1 Proposed DfT Architecture ...................... 19 3.1.2 Proposed SC/DC ........................... 21 3.1.3 Proposed Test Scheme ........................ 24 3.2 Improved WDR Configuration Generation Algorithm ....................... 26 3.3 Proposed Repair Hardware ....................... 33 Chapter4 Experiment Result ....................... 35 4.1 Single WBR Cell Area......................... 35 4.2 WDR Hardware Area.......................... 36 4.3 Repair Hardware Area ......................... 37 4.4 Test Cycle Comparison ......................... 38 4.5 WDR Configuration Generation Time Analysis ......................... 39 4.6 High Bandwidth Memory (HBM) Interconnects Testing ......................... 40 Chapter5 Conclusion ....................... 42 5.1 Conclusion ....................... 42 5.2 Future Work ....................... 42 References ....................... 44 | - |
| dc.language.iso | en | - |
| dc.title | 改進的晶片間互連串擾測試和修復解決方案 | zh_TW |
| dc.title | Improved Crosstalk Test and Repair Solution for Inter-Die Interconnects | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 張益興;黃炫倫;呂學坤 | zh_TW |
| dc.contributor.oralexamcommittee | Yi-Shing Chang;Xuan-Lun Huang;Shyue-Kung Lu | en |
| dc.subject.keyword | 三維積體電路,互連測試,可測試性設計,修復電路,串擾故障, | zh_TW |
| dc.subject.keyword | 3D-IC,Interconnect Testing,Design for Testability,Repair Circuit,Crosstalk Fault, | en |
| dc.relation.page | 48 | - |
| dc.identifier.doi | 10.6342/NTU202401758 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2024-08-02 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 積體電路設計與自動化學位學程 | - |
| dc.date.embargo-lift | 2029-07-29 | - |
| 顯示於系所單位： | 積體電路設計與自動化學位學程 | |
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