建構與二維單層二硒化鎢電晶體整合的同質互補式金屬氧化物半導體反相器

Abstract

本研究主旨在於使用單層二硒化鎢（WSe2）二維材料並利用其雙極性特性製備成n型與p型場效電晶體，接著探討兩者在製程整合上的兼容性，進而發展成WSe2互補式金屬氧化物半導體（CMOS）反相器（Inverter），以實現表現優異、匹配良好（Well-match）的電壓轉移特性（VTC）。 首先，本實驗是利用功函數與二硒化鎢之電子親和力匹配之半金屬銻（Sb）作為接觸電極來製備n型場效電晶體，將本為雙極性特性的二硒化鎢調變為n型半導體行為，而p型場效電晶體則是藉由三氧化鉬（MoO3）對二硒化鎢進行高濃度的電洞摻雜所製備。接著多方探討並分析n型與p型場效電晶體的製程整合性，以建構出Etching MoO3以及PMMA Barrier Layer兩種具可行性的反相器製備流程。 接著依循所建構的製程製備出基於氮化矽（SiNx）閘極基板之WSe2 CMOS反相器，並對其VTC電性進行參數萃取與分析，同時透過電晶體輸出曲線和轉移曲線來擬合並驗證VTC結果。經過大氣退火後可強化三氧化鉬之電洞摻雜效應，進而提升p型電晶體表現，使反相器的性能獲得大幅度地改善，並且操作於較理想的偏壓區域，達到匹配良好的VTC曲線，較符合標準的積體電路設計與整合規格。 最後為了減少反相器運作所產生的功耗，進一步微縮基板的等效氧化層厚度（EOT），改用高介電常數的二氧化鉿（HfO2）作為閘極基板，以降低反相器所需之供應電壓，並同樣對其VTC進行分析，發現不需經過大氣退火便能展現出表現優異且操作區域理想的反相器特性，同樣達到匹配良好的VTC結果。 本研究成果建構了利用二硒化鎢材料製備之電晶體所整合的CMOS反相器，與過去相關文獻相比，本實驗具備低供應電壓、轉態電壓匹配、高邊界雜訊特性的優勢，展現了與積體電路設計整合的可行性與應用性。

The main purpose of this research is to use a single layer of tungsten diselenide (WSe2) two-dimensional material and utilize its bipolar characteristics to fabricate n-type and p-type field effect transistors (FETs). Subsequently, the compatibility of these transistors in process integration is investigated, and then a WSe2 complementary metal oxide semiconductor (CMOS) inverter is developed to achieve excellent performance and well-matched voltage transfer characteristics (VTC). First of all, this experiment utilizes semi-metallic antimony (Sb), whose work function matches the electron affinity of WSe2, as the contact electrode to fabricate n-type field-effect transistor (NFET), and modulates the bipolar characteristic of WSe2 into an n-type semiconductor behavior. The p-type field-effect transistor (PFET) is fabricated by using molybdenum trioxide (MoO3) to achieve high-concentration hole doping in WSe2. Then, the process integration of NFET and PFET was extensively discussed and analyzed to construct two feasible inverter fabrication processes : Etching MoO3 and PMMA Barrier Layer. Next, following the constructed processes, a WSe2 CMOS inverter based on a silicon nitride (SiNx) gate substrate is fabricated. The VTC of the inverter are extracted and analyzed, and the results are fitted and validated through transistor output curve and transfer curve. Post-annealing in air enhances the p-doping effect of MoO3, significantly improving the performance of PFET. This optimization allows the inverter to operate in a more ideal bias region, achieving a well-matched VTC curve that aligns with standard integrated circuit (IC) design and integration specifications. Finally, to reduce the power consumption generated by the inverter during operation, the equivalent oxide thickness (EOT) of the substrate is further scaled, and high dielectric constant hafnium dioxide (HfO2) is used as the gate substrate to lower the required supply voltage for the inverter. The VTC analysis reveals that, even without air annealing, the inverter exhibits excellent performance and operates in an ideal region, also achieving well-matched VTC results. The result of this research is the construction of a CMOS inverter integrated with a transistor made of WSe2 material. Compared with previous related literatures, this experiment has the advantages of low supply voltage, matched transition voltage, and high noise margin. These features highlight the feasibility and applicability of integrating WSe2-based transistors into IC design.