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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/95597完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳志毅 | zh_TW |
| dc.contributor.advisor | Chih-I Wu | en |
| dc.contributor.author | 侯法蓉 | zh_TW |
| dc.contributor.author | Fa-Rong Hou | en |
| dc.date.accessioned | 2024-09-12T16:15:05Z | - |
| dc.date.available | 2024-09-13 | - |
| dc.date.copyright | 2024-09-12 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-06 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/95597 | - |
| dc.description.abstract | 本研究主旨在於使用單層二硒化鎢（WSe2）二維材料並利用其雙極性特性製備成n型與p型場效電晶體，接著探討兩者在製程整合上的兼容性，進而發展成WSe2互補式金屬氧化物半導體（CMOS）反相器（Inverter），以實現表現優異、匹配良好（Well-match）的電壓轉移特性（VTC）。
首先，本實驗是利用功函數與二硒化鎢之電子親和力匹配之半金屬銻（Sb）作為接觸電極來製備n型場效電晶體，將本為雙極性特性的二硒化鎢調變為n型半導體行為，而p型場效電晶體則是藉由三氧化鉬（MoO3）對二硒化鎢進行高濃度的電洞摻雜所製備。接著多方探討並分析n型與p型場效電晶體的製程整合性，以建構出Etching MoO3以及PMMA Barrier Layer兩種具可行性的反相器製備流程。 接著依循所建構的製程製備出基於氮化矽（SiNx）閘極基板之WSe2 CMOS反相器，並對其VTC電性進行參數萃取與分析，同時透過電晶體輸出曲線和轉移曲線來擬合並驗證VTC結果。經過大氣退火後可強化三氧化鉬之電洞摻雜效應，進而提升p型電晶體表現，使反相器的性能獲得大幅度地改善，並且操作於較理想的偏壓區域，達到匹配良好的VTC曲線，較符合標準的積體電路設計與整合規格。 最後為了減少反相器運作所產生的功耗，進一步微縮基板的等效氧化層厚度（EOT），改用高介電常數的二氧化鉿（HfO2）作為閘極基板，以降低反相器所需之供應電壓，並同樣對其VTC進行分析，發現不需經過大氣退火便能展現出表現優異且操作區域理想的反相器特性，同樣達到匹配良好的VTC結果。 本研究成果建構了利用二硒化鎢材料製備之電晶體所整合的CMOS反相器，與過去相關文獻相比，本實驗具備低供應電壓、轉態電壓匹配、高邊界雜訊特性的優勢，展現了與積體電路設計整合的可行性與應用性。 | zh_TW |
| dc.description.abstract | The main purpose of this research is to use a single layer of tungsten diselenide (WSe2) two-dimensional material and utilize its bipolar characteristics to fabricate n-type and p-type field effect transistors (FETs). Subsequently, the compatibility of these transistors in process integration is investigated, and then a WSe2 complementary metal oxide semiconductor (CMOS) inverter is developed to achieve excellent performance and well-matched voltage transfer characteristics (VTC).
First of all, this experiment utilizes semi-metallic antimony (Sb), whose work function matches the electron affinity of WSe2, as the contact electrode to fabricate n-type field-effect transistor (NFET), and modulates the bipolar characteristic of WSe2 into an n-type semiconductor behavior. The p-type field-effect transistor (PFET) is fabricated by using molybdenum trioxide (MoO3) to achieve high-concentration hole doping in WSe2. Then, the process integration of NFET and PFET was extensively discussed and analyzed to construct two feasible inverter fabrication processes : Etching MoO3 and PMMA Barrier Layer. Next, following the constructed processes, a WSe2 CMOS inverter based on a silicon nitride (SiNx) gate substrate is fabricated. The VTC of the inverter are extracted and analyzed, and the results are fitted and validated through transistor output curve and transfer curve. Post-annealing in air enhances the p-doping effect of MoO3, significantly improving the performance of PFET. This optimization allows the inverter to operate in a more ideal bias region, achieving a well-matched VTC curve that aligns with standard integrated circuit (IC) design and integration specifications. Finally, to reduce the power consumption generated by the inverter during operation, the equivalent oxide thickness (EOT) of the substrate is further scaled, and high dielectric constant hafnium dioxide (HfO2) is used as the gate substrate to lower the required supply voltage for the inverter. The VTC analysis reveals that, even without air annealing, the inverter exhibits excellent performance and operates in an ideal region, also achieving well-matched VTC results. The result of this research is the construction of a CMOS inverter integrated with a transistor made of WSe2 material. Compared with previous related literatures, this experiment has the advantages of low supply voltage, matched transition voltage, and high noise margin. These features highlight the feasibility and applicability of integrating WSe2-based transistors into IC design. | en |
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| dc.description.tableofcontents | 致謝 ............................................................................................................................................. i
摘要 ........................................................................................................................................... iii Abstract ..................................................................................................................................... iv 目次 ........................................................................................................................................... vi 圖次 ............................................................................................................................................ x 表次 .......................................................................................................................................... xv 第一章 緒論 .............................................................................................................................. 1 1.1 二維材料簡介 ............................................................................................................. 1 1.1.1 半導體摩爾定律之發展瓶頸 .......................................................................... 1 1.1.2 二維材料之背景與發展 .................................................................................. 4 1.1.3 二維材料之特性與優勢 .................................................................................. 6 1.1.4 二維材料製備方式 .......................................................................................... 8 1.2 過渡金屬二硫族化合物簡介 ................................................................................... 10 1.2.1 過渡金屬二硫化物結構與基本特性 ............................................................ 10 1.2.2 二硒化鎢結構與光學特性 ............................................................................ 13 1.2.3 二硒化鎢雙極性特性 .................................................................................... 16 1.3 互補式金屬氧化物半導體反相器簡介 ................................................................... 22 1.3.1 反相器之類型與發展介紹 ............................................................................ 22 1.3.2 CMOS反相器之元件結構與基礎原理......................................................... 25 1.4 研究動機 ................................................................................................................... 27 第二章 實驗方法與理論 ........................................................................................................ 29 2.1 製程儀器 ................................................................................................................... 29 2.1.1 原子層沉積系統 ............................................................................................ 29 2.1.2 低壓化學氣相沉積系統 ................................................................................ 31 2.1.3 快速熱退火 .................................................................................................... 32 2.1.4 無光罩式步進式曝光機 ................................................................................ 34 2.1.5 （電子/氦離子束）微影製程 ....................................................................... 36 2.1.6 電子束蒸鍍機 ................................................................................................ 39 2.2 量測儀器 ................................................................................................................... 41 2.2.1 光致發光及拉曼光譜分析儀 ........................................................................ 41 2.2.2 原子力顯微鏡 ................................................................................................ 43 2.2.3 橢圓偏振儀 .................................................................................................... 45 2.2.4 電性量測系統 ................................................................................................ 47 2.2.5 穿透式電子顯微鏡 ........................................................................................ 48 2.3 濕式轉移單層二硒化鎢 ........................................................................................... 49 2.4 場效電晶體電性參數萃取方法 ............................................................................... 51 2.4.1 臨界電壓 ........................................................................................................ 51 2.4.2 場效遷移率 .................................................................................................... 53 2.4.3 次臨界擺幅、電流開關比、閘極漏電流 .................................................... 53 2.4.4 介電常數與氧化層電容 ................................................................................ 55 2.4.5 高介電常數材料與等效氧化層厚度 ............................................................ 57 2.5 CMOS反相器特性參數萃取方法............................................................................ 59 2.5.1 電壓轉換特性與電壓定義 ............................................................................ 59 2.5.2 電壓轉換特性之工作原理 ............................................................................ 60 2.5.3 電壓增益 ........................................................................................................ 66 2.5.4 平均靜態功耗與峰值功耗 ............................................................................ 66 2.5.5 雜訊邊界特性 ................................................................................................ 68 第三章 建立2D-CMOS反相器製程與其n/p型電晶體之特性分析 ................................. 70 3.1 雙極性二硒化鎢製成p型與n型電晶體之製備方法 ........................................... 70 3.1.1 選擇功函數與二硒化鎢匹配之接觸電極以形成n型電晶體 .................... 70 3.1.2 利用三氧化鉬對二硒化鎢進行電洞摻雜以形成p型電晶體 .................... 74 3.2 建構CMOS反相器製備流程.................................................................................. 79 3.2.1 探討Lift-off MoO3製程之可行性 ............................................................... 79 3.2.2 探討Etching MoO3製程之可行性及對二硒化鎢n/p型電晶體之影響 .... 86 3.2.3 探討利用PMMA作為MoO3阻隔層製程之可行性及對二硒化鎢n/p型電晶體之影響 .............................................................................................................. 91 3.3 二硒化鎢 n型電晶體之穩定性瓶頸 ....................................................................... 97 3.3.1 n型電晶體於大氣下退火之退化問題 .......................................................... 97 3.3.2 n型與p型電晶體之製程兼容性問題 ........................................................ 102 第四章 二硒化鎢CMOS反相器電性結果與分析............................................................. 104 4.1 大氣下退火前後之CMOS反相器電壓轉移特性................................................ 104 4.1.1 退火前後之轉態電壓變化 .......................................................................... 104 4.1.2 以電晶體輸出曲線擬合並分析反相器電壓轉移特性曲線 ...................... 108 4.1.3 以電晶體轉移曲線分析基板漏電之影響與反相器轉態區域 .................. 113 4.2 退火前後之電壓增益萃取與分析 ......................................................................... 116 4.3 退火後之雜訊邊界特性 ......................................................................................... 118 4.4 不同供應電壓下之反相器各項電性分析與比較 ................................................. 119 第五章 利用高介電常數二氧化鉿基板以優化CMOS反相器......................................... 123 5.1 二氧化鉿基板之基本特性 ..................................................................................... 123 5.2 依循PMMA阻隔層製程之n型與p型電晶體轉移特性 ................................... 126 5.3 於High-k基板之CMOS反相器電壓轉移特性 .................................................. 129 5.3.1 二氧化鉿基板之反相器電壓轉移特性結果與分析 .................................. 129 5.3.2 以電晶體輸出曲線擬合並分析反相器電壓轉移特性曲線 ...................... 132 5.4 不同供應電壓下之反相器各項電性分析與比較 ................................................. 135 5.5 Benchmark ............................................................................................................... 138 第六章 結論與未來展望 ...................................................................................................... 140 參考文獻 ................................................................................................................................ 143 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 二硒化鎢 | zh_TW |
| dc.subject | 等效氧化層厚度微縮 | zh_TW |
| dc.subject | 電壓轉移特性 | zh_TW |
| dc.subject | 互補式金屬氧化物半導體反相器 | zh_TW |
| dc.subject | 同質 | zh_TW |
| dc.subject | 製程兼容性與整合性 | zh_TW |
| dc.subject | 電洞摻雜 | zh_TW |
| dc.subject | 三氧化鉬 | zh_TW |
| dc.subject | p型場效電晶體 | zh_TW |
| dc.subject | 半金屬銻 | zh_TW |
| dc.subject | n型場效電晶體 | zh_TW |
| dc.subject | 二維材料 | zh_TW |
| dc.subject | Equivalent oxide thickness (EOT) scaling | en |
| dc.subject | Two-dimensional (2D) materials | en |
| dc.subject | Tungsten diselenide (WSe2) | en |
| dc.subject | N-type Field effect transistor (NFET) | en |
| dc.subject | Semi-metal Antimony (Sb) | en |
| dc.subject | P-type Field effect transistor (PFET) | en |
| dc.subject | Molybdenum trioxide (MoO3) | en |
| dc.subject | hole doping (p-doping) | en |
| dc.subject | Process compatibility and integration | en |
| dc.subject | Homogeneous | en |
| dc.subject | Complementary metal oxide semiconductor inverters (CMOS Inverter) | en |
| dc.subject | Voltage transfer characteristics (VTC) | en |
| dc.title | 建構與二維單層二硒化鎢電晶體整合的同質互補式金屬氧化物半導體反相器 | zh_TW |
| dc.title | Construction of a homogeneous CMOS inverter integrated with two-dimensional monolayer WSe2 transistors | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳奕君;張子璿;吳肇欣;周昂昇 | zh_TW |
| dc.contributor.oralexamcommittee | I-Chun Cheng;Tzu-Hsuan Chang;Chao-Hsin Wu;Ang-Sheng Chou | en |
| dc.subject.keyword | 二維材料,二硒化鎢,n型場效電晶體,半金屬銻,p型場效電晶體,三氧化鉬,電洞摻雜,製程兼容性與整合性,同質,互補式金屬氧化物半導體反相器,電壓轉移特性,等效氧化層厚度微縮, | zh_TW |
| dc.subject.keyword | Two-dimensional (2D) materials,Tungsten diselenide (WSe2),N-type Field effect transistor (NFET),Semi-metal Antimony (Sb),P-type Field effect transistor (PFET),Molybdenum trioxide (MoO3),hole doping (p-doping),Process compatibility and integration,Homogeneous,Complementary metal oxide semiconductor inverters (CMOS Inverter),Voltage transfer characteristics (VTC),Equivalent oxide thickness (EOT) scaling, | en |
| dc.relation.page | 149 | - |
| dc.identifier.doi | 10.6342/NTU202403082 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2024-08-10 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2029-08-01 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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