應用於分頻雙工通訊系統之 CMOS 自干擾消除接收機

Abstract

下世代的無線通訊發展中，更高的資料傳輸量是主要追求的目標，為了盡可能地提高頻譜使用效率以達到更高的資料通行量，分頻雙工的傳輸方法被廣泛運用於無線通訊系統。然而，分頻雙工的傳輸系統所面臨的自干擾問題是此類系統的一大挑戰。因此，如何在提高資料量的同時減緩自干擾問題，並降低額外設計成本是本篇的設計目的。 本篇提出的自干擾消除接收機，利用晶片內部的前饋路徑，以兩路消除的方式將干擾訊號做主動式消除，有別於被動式濾波的方法並能與之相結合，透過控制兩路徑訊號的傳輸時間，達到自干擾消除的效果。消除路徑設計於第一級低雜訊放大器之後，降低其對整體系統雜訊的影響，透過使用低功耗的混頻器及基頻放大器，讓消除路徑所需的成本大幅降低。 這個由 0.18 微米 CMOS 製程實作之自干擾消除接收機，應用於分頻雙工系統，操作於 5G NR Upper 6 GHz (6.425 – 7.125 GHz) 頻段，由晶片量測結果可驗證所提出電路的功能性，面對最高 -20 dBm 的干擾訊號，在訊號帶寬 120 MHz，200 MHz的頻率間距下，達到 32 dB 的自干擾消除效果，在 1.8 V 的電源供應下，消耗 24.1 mW 的功耗。

In the development of next-generation wireless communication, achieving higher data transmission rates is a primary goal. To maximize spectrum efficiency and achieve higher data throughput, frequency-division duplexing (FDD) transmission methods are widely used in wireless communication systems. However, the self-interference problem faced by FDD transmission systems is a major challenge. Therefore, the aim of this work is to mitigate self-interference issues while increasing data rates and minimizing additional design costs. The proposed self-interference cancellation receiver utilizes an on-chip feedforward path to actively cancel interference signals in a dual-path manner, distinguishing itself from passive filtering methods and allowing for integration with them. By controlling the transmission time of signals in both paths, the desired self-interference cancellation effect is achieved. The cancellation path is designed after the first-stage low-noise amplifier, reducing its impact on the overall system noise. Through the use of low-power mixers and baseband amplifiers, the cost of the cancellation path is significantly reduced. The proposed self-interference cancellation receiver for FDD operation, implemented in a 0.18 $um$ CMOS process, operates in the 5G NR Upper 6 GHz (6.425 – 7.125 GHz) band. Chip measurement results validate the functionality of the proposed circuit. In the presence of interference signals up to -20 dBm, it achieves a self-interference cancellation of 32 dB with signal bandwidths of 120 MHz and frequency offset of 200 MHz. With a 1.8 V power supply, it consumes 24.1 mW of DC power.