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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/94873完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂良鴻 | zh_TW |
| dc.contributor.advisor | Liang-Hung Lu | en |
| dc.contributor.author | 張亦捷 | zh_TW |
| dc.contributor.author | Yi-Chieh Chang | en |
| dc.date.accessioned | 2024-08-20T16:20:00Z | - |
| dc.date.available | 2024-08-21 | - |
| dc.date.copyright | 2024-08-20 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-08 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/94873 | - |
| dc.description.abstract | 下世代的無線通訊發展中，更高的資料傳輸量是主要追求的目標，為了盡可能地提高頻譜使用效率以達到更高的資料通行量，分頻雙工的傳輸方法被廣泛運用於無線通訊系統。然而，分頻雙工的傳輸系統所面臨的自干擾問題是此類系統的一大挑戰。因此，如何在提高資料量的同時減緩自干擾問題，並降低額外設計成本是本篇的設計目的。
本篇提出的自干擾消除接收機，利用晶片內部的前饋路徑，以兩路消除的方式將干擾訊號做主動式消除，有別於被動式濾波的方法並能與之相結合，透過控制兩路徑訊號的傳輸時間，達到自干擾消除的效果。消除路徑設計於第一級低雜訊放大器之後，降低其對整體系統雜訊的影響，透過使用低功耗的混頻器及基頻放大器，讓消除路徑所需的成本大幅降低。 這個由 0.18 微米 CMOS 製程實作之自干擾消除接收機，應用於分頻雙工系統，操作於 5G NR Upper 6 GHz (6.425 – 7.125 GHz) 頻段，由晶片量測結果可驗證所提出電路的功能性，面對最高 -20 dBm 的干擾訊號，在訊號帶寬 120 MHz，200 MHz的頻率間距下，達到 32 dB 的自干擾消除效果，在 1.8 V 的電源供應下，消耗 24.1 mW 的功耗。 | zh_TW |
| dc.description.abstract | In the development of next-generation wireless communication, achieving higher data transmission rates is a primary goal. To maximize spectrum efficiency and achieve higher data throughput, frequency-division duplexing (FDD) transmission methods are widely used in wireless communication systems. However, the self-interference problem faced by FDD transmission systems is a major challenge. Therefore, the aim of this work is to mitigate self-interference issues while increasing data rates and minimizing additional design costs.
The proposed self-interference cancellation receiver utilizes an on-chip feedforward path to actively cancel interference signals in a dual-path manner, distinguishing itself from passive filtering methods and allowing for integration with them. By controlling the transmission time of signals in both paths, the desired self-interference cancellation effect is achieved. The cancellation path is designed after the first-stage low-noise amplifier, reducing its impact on the overall system noise. Through the use of low-power mixers and baseband amplifiers, the cost of the cancellation path is significantly reduced. The proposed self-interference cancellation receiver for FDD operation, implemented in a 0.18 $um$ CMOS process, operates in the 5G NR Upper 6 GHz (6.425 – 7.125 GHz) band. Chip measurement results validate the functionality of the proposed circuit. In the presence of interference signals up to -20 dBm, it achieves a self-interference cancellation of 32 dB with signal bandwidths of 120 MHz and frequency offset of 200 MHz. With a 1.8 V power supply, it consumes 24.1 mW of DC power. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-20T16:20:00Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-20T16:20:00Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Approval i
Acknowledgement iii Chinese Abstract v Abstract vii List of Figures xi List of Tables xv 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Introduction to SIC Receiver 5 2.1 Receiver for Wireless Communication System . . . . . . . . . . . . . . . 5 2.1.1 Heterodyne Receivers . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.2 Direct Conversion Receivers . . . . . . . . . . . . . . . . . . . . 6 2.1.3 Low-IF Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Receiver Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 Low Noise Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Variable Gain Amplifiers . . . . . . . . . . . . . . . . . . . . . . 12 2.2.4 On-Chip Transformers . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Fundamentals of Self-Interference Cancellation . . . . . . . . . . . . . . 15 2.3.1 Full-Duplex and Frequency-Division Duplexing . . . . . . . . . . 15 2.3.2 Self-Interference Problem . . . . . . . . . . . . . . . . . . . . . 17 2.3.3 Self-Interference Cancellation . . . . . . . . . . . . . . . . . . . 18 3 Proposed SIC Receiver 23 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 System Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.1 Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.2 Self-Interference Cancellation Path . . . . . . . . . . . . . . . . 41 3.4.3 Automatic Gain Control Loop . . . . . . . . . . . . . . . . . . . 45 3.4.4 Transmission Gate and RF Buffer . . . . . . . . . . . . . . . . . 51 3.4.5 RF Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.6 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.4.7 LO Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4.8 Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . 57 3.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.5.1 Generic Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5.2 SIC Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4 Experimental Results 71 4.1 PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2 Measurement Setups and Experimental Results . . . . . . . . . . . . . . 74 4.2.1 DC Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.2.2 Generic Receiver Measurement . . . . . . . . . . . . . . . . . . 75 4.2.3 SIC Receiver Measurement . . . . . . . . . . . . . . . . . . . . 81 4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5 Conclusion 87 Reference 91 | - |
| dc.language.iso | en | - |
| dc.subject | 前饋技術 | zh_TW |
| dc.subject | 互補式金屬氧化物半導體 | zh_TW |
| dc.subject | 接收機 | zh_TW |
| dc.subject | 自干擾消除 | zh_TW |
| dc.subject | 分頻雙工 | zh_TW |
| dc.subject | frequency-division duplexing (FDD) | en |
| dc.subject | selfinterference cancellation (SIC) | en |
| dc.subject | receiver | en |
| dc.subject | feedforward technique | en |
| dc.subject | CMOS | en |
| dc.title | 應用於分頻雙工通訊系統之 CMOS 自干擾消除接收機 | zh_TW |
| dc.title | A CMOS Self-Interference Cancellation Receiver for Frequency-Division Duplexing Communication Systems | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳怡然;陳巍仁 | zh_TW |
| dc.contributor.oralexamcommittee | Yi-Jan Chen;Wei-Zen Chen | en |
| dc.subject.keyword | 互補式金屬氧化物半導體,前饋技術,分頻雙工,自干擾消除,接收機, | zh_TW |
| dc.subject.keyword | CMOS,feedforward technique,frequency-division duplexing (FDD),selfinterference cancellation (SIC),receiver, | en |
| dc.relation.page | 94 | - |
| dc.identifier.doi | 10.6342/NTU202403856 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-08-12 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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