工程改變命令補丁生成的最佳矯正點選擇

Abstract

本論文主要探討現代超大規模積體電路(VLSI)設計中工程改變命令(ECO)的問題。由於功能問題和規格變更在設計過程中難以避免，尤其是在接近量產階段時，高效的 ECO 技術對於及時、準確地進行設計修正至關重要，同時避免重複進行邏輯綜合和時序驗證等複雜流程。本研究著重於 ECO 過程的自動化和優化，特別是在選擇和驗證修正區域方面。我們採用改進後基於全稱量詞消除的方法來優化的 ECO 公式。此方法能有效利用 SAT 求解器進行驗證，並探索多樣化的解決方案。我們的主要貢獻在於提出了一種系統性方法來評估和選擇修正區域，從而能夠生成高質量的修補程式。該算法旨在識別多樣化的潛在解法，並確定最佳的修補組合，展示了這種優化方法如何顯著提高 VLSI 設計中 ECO 過程的效率和有效性。通過解決修正區域選擇和驗證的長期挑戰，我們的工作為晶片設計優化的廣泛領域做出了改進。

This thesis addresses the critical challenge of Functional Engineering Change Order (ECO) in modern VLSI design. As functional problems and specification changes are inevitable, especially near the tape-out stage, efficient ECO technology is crucial for timely and accurate design corrections without repeating complex processes like logic synthesis and timing verification. The research focuses on automating and optimizing the ECO process, particularly in selecting and verifying rectification regions. We present an innovative algorithm that employs an improved quantifier-elimination based approach for ECO formula manipulation. This method efficiently utilizes SAT solvers for verification and explores a wide variety of solutions. Our key contribution is a systematic approach to evaluating and selecting rectification regions, which enables the generation of high-quality patches. The algorithm is designed to identify diverse potential solutions and determine the optimal combination for patch generation. This approach not only minimizes the risk of overlooking errors but also ensures the maintenance of tight production schedules, which is critical in preventing market entry delays. The thesis demonstrates how this advanced methodology can enhance the efficiency and effectiveness of the ECO process in VLSI design. By addressing the long-standing challenges in rectification region selection and verification, our work contributes to the broader field of chip design optimization.