一個使用週期性轉導放大器共享技巧之13.8有效位元二階CIFF雜訊整形連續漸進式類比數位轉換器

Abstract

在這篇論文，將討論在於物聯網應用中，設計類比讀出電路在此應用下的挑戰。在晶片設計中，透過結合逐次逼近之類比數位轉換器和三角積分調變器，實現了一種混和式的架構，使讀出電路同時具有低功耗和雜訊整形的效果，再利用超取樣使頻寬內的量化雜訊可以大幅下降並減少因取樣電路中的kT/C雜訊、不匹配和比較器雜訊引起的解析度損失，從而克服以上兩種架構在設計上的困難。 電路實現具有2 MS/s取樣頻率和62.5 kHz輸入信號頻寬的雜訊整形讀出電路。架構上採用了串級積分器前授 (CIFF) 架構，並通過週期性驅動轉導放大器的運作時間降低迴路濾波器的功耗，並完成量化雜訊的逐次積分，從而實現二階雜訊整形。此外，本論文還引入了一種具有源級隨耦器輸出級和低雜訊的緩衝器，透過輸出級複製的技巧將電路中的負迴授輸出轉為開迴路，使電路在量化過程中，避免因大電容充放電的行為引起的參考電壓抖動及不穩定性。 這次的晶片設計使用了十位元的逐次逼近類比數位轉換器作為量化器的核心電路，並取16倍的超取樣率，透過共享一級積分器實現二階雜訊整形，最終達到了13.8位的解析度。晶片採用台積電90 nm CMOS技術製造，在2 MS/s的操作速度下僅消耗108 μW。在晶片的性能表現上達到了172.4 dB的性能指標 (FoMs) ，84.8 dB的訊號雜訊失真比 (SNDR) 和86 dB的動態範圍 (DR)。

This thesis introduces an analog front-end (AFE) system and readout circuit designed for Internet of Things (IoT) sensors. The ADC utilizes a novel hybrid architecture that combines SAR ADC and delta-sigma ADC technologies to achieve both power efficiency and high resolution. By employing noise-shaping and oversampling techniques, we effectively reduce quantization noise and minimize the impact of kT/C noise, mismatch, and comparator noise, optimizing bandwidth through an increased Oversampling Ratio (OSR). In this research, we present a 2MS/s, 62.5kHz bandwidth NS-SAR ADC with a hardware-efficient design. A second-order noise-shaping mechanism is realized using a duty-cycled Operational Transconductance Amplifier (OTA) in a time-sharing approach. The design incorporates a CIFF structure and a system robust against PVT variations in a closed-loop configuration. Additionally, a reference buffer with a replicated source follower output stage and noise cancellation is proposed to reduce the loading effect on the internal feedback loop. The NS-SAR ADC achieves a resolution of 13.8 bits, utilizing a 10-bit core SAR ADC and an OSR of 16. Fabricated using 90 nm CMOS technology, the prototype operates at 2MS/s and consumes only 108 μW. This NS-SAR implementation achieves a peak Schreier Figure of Merit (FoMs) of 172.4 dB, an SNDR of 84.8 dB, and a dynamic range of 86 dB.