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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93492完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | zh_TW |
| dc.contributor.advisor | Tsung-Hsien Lin | en |
| dc.contributor.author | 王昱翔 | zh_TW |
| dc.contributor.author | Yu-Hsiang Wang | en |
| dc.date.accessioned | 2024-08-05T16:11:32Z | - |
| dc.date.available | 2024-08-06 | - |
| dc.date.copyright | 2024-08-05 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-07-16 | - |
| dc.identifier.citation | References
[1] A. Nikoukar, S. Raza, A. Poole, M. Güneş and B. Dezfouli, "Low-Power Wireless for the Internet of Things: Standards and Applications," IEEE Access, vol. 6, pp. 67893-67926, Nov. 2018. [2] J. Gubbi, R. Buyya, S. Marusic, and M. Palaniswami, "Internet of Things (IoT): A Vision, Architectural Elements, and Future Directions," Future Generation. Comput. Syst., vol. 29, no. 7, pp. 1645-1660, Jul. 2013. [3] R. Schreier and G. C. Temes, "Understanding Delta-Sigma Data Converters," Wiley, 2005. [4] L. Jie et al., "An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier," IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 149-161, Oct. 2021. [5] S. Li, "A kT/C-Noise-Cancelled Noise-Shaping SAR ADC with a Duty-Cycled Amplifier," IEEE 63rd International Midwest Symposium on Circuits and Systems, pp. 758-761, Sep. 2020. [6] T.-H. Wang, R. Wu, V. Gupta, X. Tang and S. Li, "A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure with Hardware-Reusing kT/C Noise Cancellation," IEEE Journal of Solid-State Circuits, vol. 56, no. 12, pp. 3668-3680, Dec. 2021. [7] X. Tang et al., "A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier," IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3248-3259, Dec. 2020. [8] J. Liu, D. Li, Y. Zhong, X. Tang, and N. Sun, "27.1 A 250 kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering," IEEE International Solid-State Circuits Conference, pp. 369-371, Mar. 2021. [9] T. Kim and Y. Chae, "A 2.1 mW 2 MHz-BW 73.8 dB-SNDR Buffer-Embedded Noise-Shaping SAR ADC," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 12, pp. 5029-5037, Dec. 2021. [10] K. Obata, K. Matsukawa, T. Miki, Y. Tsukamoto, and K. Sushihara, "A 97.99 dB SNDR, 2 kHz BW, 37.1 µW Noise-Shaping SAR ADC with Dynamic Element Matching and Modulation Dither Effect," IEEE Symposium on VLSI Circuits, pp. 1-2, Sep. 2016. [11] T. Wang, T. Xie, Z. Liu and S. Li, "An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique," IEEE International Solid-State Circuits Conference, pp. 418-420, Mar. 2022. [12] C.-A. Gobet and A. Knob, "Noise Analysis of Switched-Capacitor Networks," IEEE Transactions on Circuits and Systems, vol. 30, no. 1, pp. 37-43, Jan. 1983. [13] R. Schreier, J. Silva, J. Steensgaard and G. C. Temes, "Design-Oriented Estimation of Thermal Noise in Switched-Capacitor Circuits," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2358-2368, Nov. 2005. [14] S. Li, B. Qiao, M. Gandara, D. Z. Pan, and N. Sun, "A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure," IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3484-3496, Dec. 2018. [15] H. Zhuang et al., "A Second-Order Noise-Shaping SAR ADC with Passive Integrator and Tri-Level Voting," IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1636-1647, Jun. 2019. [16] J. Liu et al., "A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping," IEEE Journal of Solid-State Circuits, vol. 56, no. 11, pp. 3412-3423, Nov. 2021. [17] C.-C. Liu et al., "A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation," IEEE International Solid-State Circuits Conference, pp. 386-387, Mar. 2010. [18] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink and B. Nauta, "A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s," IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. [19] E. Zimmermann, A. Verweerd, W. Glaas, A. Tillmann and A. Kemna, "An AMR Sensor-Based Measurement System for Magnetoelectrical Resistivity Tomography," IEEE Sensors Journal, vol. 5, no. 2, pp. 233-241, Apr. 2005. [20] T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, "Noise Analysis for Comparator-Based Circuits," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 3, pp. 541-553, Mar. 2009. [21] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, "A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. [22] C. Liu, C. Kuo, and Y. Lin, "A 10-bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 50, no. 11, pp. 2645-2654, Nov. 2015. [23] H. Li, Y. Shen, H. Xin, E. Cantatore, and P. Harpe, "A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Mismatch Error Shaping," IEEE Journal of Solid-State Circuits, vol. 57, no. 7, pp. 2078-2089, Jul. 2022. [24] C.-k. Lee, W. Kim, H. Kang and S.-T. Ryu, "A Replica-Driving Technique for High-Performance SC Circuits and Pipelined ADC Design," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 9, pp. 557-561, Sep. 2013. [25] P. Harikumar and J. J. Wikner, "Design of a Reference Voltage Buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS," IEEE International Symposium on Circuits and Systems, pp. 249-252, Jul. 2015. [26] X. Liu, C. Zhan and H. Qiao, "Chip-Area-Efficient Capacitor-less LDO Regulator with Fast-Transient Response," IEEE International Conference on Integrated Circuits, Technologies and Applications, pp. 27-28, Feb. 2019. [27] S.-W. M. Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13- μm CMOS," IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006. [28] H. Garvik, C. Wulff and T. Ytterdal, "An 11.0 bit ENOB, 9.8 fJ/conv.-step Noise-Shaping SAR ADC Calibrated by Least Squares Estimation," IEEE Custom Integrated Circuits Conference, pp. 1-4, Jul. 2017. [29] Q. Zhang et al., "A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration," IEEE Journal of Solid-State Circuits, vol. 57, no. 7, pp. 2181-2195, Jul. 2022. [30] M. Fukazawa and T. Matsui, "A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer," IEEE Symposium on VLSI Technology and Circuits, pp. 1-2, Jul. 2023. [31] Y.-Z. Lin, C.-Y. Lin, S.-C. Tsou, C.-H. Tsai and C. -H. Lu, "20.2 A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC with Passive Signal-Residue Summation in 14nm FinFET," IEEE International Solid-State Circuits Conference, pp. 330-332, Mar. 2019. [32] Y. Shen, H. Li, H. Xin, E. Cantatore, and P. Harpe, "A 103-dB SFDR Calibration-Free Oversampled SAR ADC with Mismatch Error Shaping and Pre-Comparison Techniques," IEEE Journal of Solid-State Circuits, vol. 57, no. 3, pp. 734-744, Mar. 2022. [33] Y.-S. Shu, L.-T. Kuo and T.-Y. Lo, "An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2928-2940, Dec. 2016. [34] H. Li, Y. Shen, E. Cantatore, and P. Harpe, "A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator, "IEEE Symposium on VLSI Technology and Circuits, pp. 58-59, Jul. 2022. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93492 | - |
| dc.description.abstract | 在這篇論文，將討論在於物聯網應用中，設計類比讀出電路在此應用下的挑戰。在晶片設計中，透過結合逐次逼近之類比數位轉換器和三角積分調變器，實現了一種混和式的架構，使讀出電路同時具有低功耗和雜訊整形的效果，再利用超取樣使頻寬內的量化雜訊可以大幅下降並減少因取樣電路中的kT/C雜訊、不匹配和比較器雜訊引起的解析度損失，從而克服以上兩種架構在設計上的困難。
電路實現具有2 MS/s取樣頻率和62.5 kHz輸入信號頻寬的雜訊整形讀出電路。架構上採用了串級積分器前授 (CIFF) 架構，並通過週期性驅動轉導放大器的運作時間降低迴路濾波器的功耗，並完成量化雜訊的逐次積分，從而實現二階雜訊整形。此外，本論文還引入了一種具有源級隨耦器輸出級和低雜訊的緩衝器，透過輸出級複製的技巧將電路中的負迴授輸出轉為開迴路，使電路在量化過程中，避免因大電容充放電的行為引起的參考電壓抖動及不穩定性。 這次的晶片設計使用了十位元的逐次逼近類比數位轉換器作為量化器的核心電路，並取16倍的超取樣率，透過共享一級積分器實現二階雜訊整形，最終達到了13.8位的解析度。晶片採用台積電90 nm CMOS技術製造，在2 MS/s的操作速度下僅消耗108 μW。在晶片的性能表現上達到了172.4 dB的性能指標 (FoMs) ，84.8 dB的訊號雜訊失真比 (SNDR) 和86 dB的動態範圍 (DR)。 | zh_TW |
| dc.description.abstract | This thesis introduces an analog front-end (AFE) system and readout circuit designed for Internet of Things (IoT) sensors. The ADC utilizes a novel hybrid architecture that combines SAR ADC and delta-sigma ADC technologies to achieve both power efficiency and high resolution. By employing noise-shaping and oversampling techniques, we effectively reduce quantization noise and minimize the impact of kT/C noise, mismatch, and comparator noise, optimizing bandwidth through an increased Oversampling Ratio (OSR).
In this research, we present a 2MS/s, 62.5kHz bandwidth NS-SAR ADC with a hardware-efficient design. A second-order noise-shaping mechanism is realized using a duty-cycled Operational Transconductance Amplifier (OTA) in a time-sharing approach. The design incorporates a CIFF structure and a system robust against PVT variations in a closed-loop configuration. Additionally, a reference buffer with a replicated source follower output stage and noise cancellation is proposed to reduce the loading effect on the internal feedback loop. The NS-SAR ADC achieves a resolution of 13.8 bits, utilizing a 10-bit core SAR ADC and an OSR of 16. Fabricated using 90 nm CMOS technology, the prototype operates at 2MS/s and consumes only 108 μW. This NS-SAR implementation achieves a peak Schreier Figure of Merit (FoMs) of 172.4 dB, an SNDR of 84.8 dB, and a dynamic range of 86 dB. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-05T16:11:32Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-05T16:11:32Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Table of Contents
論文口試委員會審定書 i 摘要 v Abstract vii List of Figures xi List of Tables xiv Chapter 1 Introduction 1 1.1 Background 1 1.2 Dissertation Overview 3 Chapter 2 Fundamental of NS-SAR ADC 5 2.1 Structure of Noise-Shaping SAR ADC 5 2.2 Loop Filter of Noise-Shaping SAR ADC 11 2.3 Discussion and Summary 13 Chapter 3 Noise Analysis of Switched-capacitor Integrator and Design Flow 14 3.1 Noise Character in SC Integrator 14 3.2 Noise Analysis in Each Phase of SC Integrator 18 3.3 Discussion and Summary 23 Chapter 4 Design of a 2nd-order NS-SAR ADC with Duty-Cycled OTA Sharing Technique 24 4.1 Introduction 24 4.2 System Architecture 28 4.2.1 System Coefficient 30 4.3 Circuit Implementation 32 4.3.1 Bootstrapped Switch 33 4.3.2 Two-stage Dynamic Comparator 35 4.3.3 CDAC 37 4.3.4 SAR Control Logic 39 4.3.5 Loop Filter 44 4.3.6 Pulse Generator 52 4.3.7 Reference Buffer 53 4.4 Discussion and Summary 56 Chapter 5 Measurement Results 57 5.1 Die photo 57 5.2 Measurement Environment Setup 57 5.3 Measured Results 60 5.4 Discussion and Summary 67 Chapter 6 Conclusions and Future Works 68 6.1 Conclusions 68 6.2 Future Works 69 References 71 | - |
| dc.language.iso | en | - |
| dc.title | 一個使用週期性轉導放大器共享技巧之13.8有效位元二階CIFF雜訊整形連續漸進式類比數位轉換器 | zh_TW |
| dc.title | Design of a 13.8-ENOB 2nd-order CIFF Noise-Shaping SAR ADC with Duty-Cycled OTA Sharing Technique | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 鍾勇輝;許雲翔;李泰成;劉深淵 | zh_TW |
| dc.contributor.oralexamcommittee | Yung-Hui Chung;Yun-Shiang Shu;Tai-Cheng Lee;Shen-Iuan Liu | en |
| dc.subject.keyword | 前端讀出電路,感測器,數位類比轉換器,雜訊整形,抵抗製程變異,逐次逼近,類比數位轉換器, | zh_TW |
| dc.subject.keyword | Analog Front-End (AFE),Sensor,Digital-to-Analog Converter (DAC),Noise-Shaping,PVT Robust,SAR ADC,Analog-to-Digital Converter (ADC), | en |
| dc.relation.page | 76 | - |
| dc.identifier.doi | 10.6342/NTU202401800 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2024-07-17 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2029-07-15 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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