應用於毫米波頻段之八百億赫茲鎖相迴路

Abstract

本論文提出應用於毫米波頻段之八百億赫茲鎖相迴路，其主要功能是將輸出頻率鎖定在輸入參考信號的倍頻頻率上，並將輸出相位與輸入參考信號相位對齊，以提供可在晶片內實現的時脈。 本篇一共實作了兩個電路。第一顆晶片為一操作在毫米波頻段之九百億赫茲壓控振盪器，此晶片實作於台積電40奈米製程。採用模式切換雙核耦合之架構，利用電感互感的原理，透過切換開關來改變核心電路所看到的等效電感值，以實現切換頻段(粗調)的功能。在頻率細調方面，將電晶體作為可變電容，通過改變電壓來調整核心電路之等效電容值。晶片核心面積為0.021平方毫米，整體功耗為39.8毫瓦特，頻率可調整範圍為4.5 %，在一千萬赫茲頻率偏移處之相位雜訊為 -105.8 dBc/Hz，一千萬赫茲頻率偏移處之品質因數為 -169.4 dBc/Hz。 第二顆晶片實作八百億赫茲之鎖相迴路，此晶片實作於台積電40奈米製程。架構採用傳統第二型電荷泵浦鎖相迴路，其好處為操作較具韌性。除頻鏈的部分，除數為400，採用四級除以二的除頻電路串接兩級除以五的除頻電路，其中四級除以二的除頻電路為兩級注入鎖定除頻器、一級主樸式偶合閘除頻器以及一級真單相時脈除頻器，其架構設計受電路操作頻率的影響。晶片核心面積為0.4128平方毫米，整體功耗為38.3毫瓦特，在頻率偏移分別為一百萬赫茲和一千萬赫茲時，相位雜訊分別為-82 dBc/Hz和-107.2 dBc/Hz。抖動從一萬赫茲偏移處積分到一億赫茲偏移處為355飛秒，在品質因數方面， FoM @ 10MHz = -170 dBc/Hz及 FoM-jitter = -233.2。

This thesis proposes an 80-GHz phase-locked loop (PLL) designed for millimeter-wave application, aiming to lock the output frequency to a multiple of the input reference signal and align the output phase with the input signal, providing an on-chip clock. In this thesis, two circuits have been implemented. The first chip is a 90-GHz voltage-controlled oscillator (VCO), fabricated in a TSMC 40-nm process. It employs a mode-switching dual-core-coupled architecture based on inductive coupling. For coarse tuning, switches are used to vary the effective inductance values. Fine-tuning is achieved by utilizing transistors as varactors to modify the effective capacitance values. The core area of this chip is 0.021 mm2, with a total power consumption of 39.8 mW. The frequency tuning range is 4.5 %. The phase noise at a 10 MHz offset is -105.8 dBc/Hz, and the figure of merit (FoM) at a 10 MHz offset is -169.4 dBc/Hz. The second one, also fabricated in a TSMC 40-nm process, implements an 80-GHz phase-locked loop (PLL) based on a conventional Type-II charge-pump PLL(CPPLL) architecture, known for its robust operation. It features a division factor of 400 and consists of four stages of divide-by-two circuits cascaded by two stages of divide-by-five circuits. The architecture is chosen based on the operating frequency of the circuit. The core area of this chip is 0.33 mm2 with a power consumption of 38.3 mW. The phase noise at 1 MHz and 10 MHz offset are -82 dBc/Hz and -107.2 dBc/Hz, respectively. The integrated jitter from 10 kHz to 100 MHz offset is 355 fs. The FoM @ 10MHz is -170 dBc/Hz, and the FoM-jitter is -233.2.