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標題: | 具高介電常數氧化鋁與氧化矽堆疊結構金氧半元件多位階電荷儲存及暫態記憶特性之研究 Study of Multiple Charge-Storage States and Transient Memory Behaviors in MIS(p) with High-k Al2O3/SiO2 Stacking Structure |
作者: | 羅雅云 Ya-Yun Lo |
指導教授: | 胡振國 Jenn-Gwo Hwu |
關鍵字: | 高介電常數材料堆疊結構,金氧半電容元件,多位階電荷儲存,平帶電壓,暫態行為,金屬後退火, high dielectric constant (high-k) material stacking structure,metal-insulator-semiconductor (MIS) capacitor,multi-level charge-storage states,flat-band voltages,transient behaviors,post-metallization-annealing (PMA), |
出版年 : | 2024 |
學位: | 碩士 |
摘要: | 本篇論文主要在探討高介電常數材料對金氧半電容元件的基本電特性及記憶體應用中電荷儲存性能之影響。有別於傳統平面金氧半穿隧二極體,我們在氧化矽上堆疊兩層高介電材料氧化鋁,形成一具高介電氧化物之金氧半電容元件。在這個元件中,氧化鋁層扮演電荷捕捉及儲存材料的角色,實現此元件多位階電荷記憶特性之應用。在加入高介電材料層之後,金氧半元件的性質和行為會產生許多變化。在電性方面,因為絕緣層整體厚度增加,電流級距因穿隧機率下降而變小,進而導致位移電流的效應變得更加明顯。此外,在相反電壓掃描方向的電容-電壓特性量測中,此元件呈現了兩個不同的平帶電壓值,展現其在表現元件內部不同電荷儲存情況的能力。因此,我們在元件上施加特定時間的電壓作為記憶體寫入資料的過程,並再次測量電容-電壓特性以記錄平帶電壓的變化,用以代表不同的讀取資料。而透過調整施加電壓的大小和持續時間,我們可以達到此元件多位階電荷儲存的目的。接著,我們深入探討此高介電材料金氧半元件中的暫態行為。根據元件在施加電壓之後讀取的暫態電流特性,我們可以推測其內部載子間的互動和流動方向。在施加正負電壓之後,會形成不同大小及方向的電流,利用此不同暫態行為的表現也可以作為記憶資料的應用。此外,元件在施加電壓之後電容數值會維持一段時間,也展現了其記憶資料的持續能力。而作為對照組,我們也做了一具有約十奈米厚氧化矽的金氧半元件,並探討其暫態行為。透過二維TCAD模擬工具的輔助,我們探討在施加電壓之後此元件內部電子和電洞濃度,以及載子之間復合速率隨時間的變化,來與在實驗量測中所發現的電流峰值做對照,並驗證其中載子移動與彼此互動的機制。另一方面,我們將高介電金氧半元件做金屬後退火之處理,並作相似的電性量測,探討退火消除元件內部缺陷與氧化層電荷的能力,以及此元件在退火處理之後,其記憶資料表現與暫態行為的變化。最後,經由元件製程與退火處理優化來達到具高穩定性,且特性理想的非揮發記憶體金氧半元件。 This thesis delved into the impact of high-k dielectric layers on the fundamental electrical characteristics and charge storage performance in metal-oxide-semiconductor (MIS) devices for memory applications. Different from a conventional planar MIS tunnel diode (TD) device, we stacked two layers of high-k material, Al2O3, on SiO2. The Al2O3 layers played the role of charge trapping material in this device, enabling the realization of multi-level memory states. There are various changes in the behaviors of MIS device after the introduction of high-k dielectric layers. In the aspect of changes in electrical characteristics, the current order decreased due to the thickening of insulator layers, thereby causing the effect of displacement current became more significant. Moreover, the C-V characteristics have shown distinct flat-band voltage values for opposite voltage sweeping directions, indicating the potential for representing charge storage conditions in high-k MIS. Therefore, we stressed voltage pulses as the writing data process, then reading the C-V properties again to record the variations in flat-band voltage values. Through the adjustment of pulse magnitude and pulse duration, we could obtain multiple charge storage states in this device. Furthermore, the transient behaviors in high-k MIS were investigated. For memory applications, voltage pulses were also applied on the device, then switched to a reading gate bias to read the transient current. Depending on the movement of carriers, we achieved current values with different magnitudes and directions, creating a current window for data recording. The C-t measurement exhibited that the capacitance values persisted for a certain duration of measurement, indicating the retention ability of data in this device. In addition, the transient properties of MIS device with pure thick SiO2 were explored. 2D TCAD simulation investigated the concentration of electron and hole, as well as the recombination rate in silicon substrate after negative voltage pulsing. This analysis clarified the I-t properties and interaction between carriers in this device. On the other hand, we subjected the high-k MIS to post-metallization-annealing (PMA), followed by similar measurements, including memory window performance and transient behaviors investigation. Since PMA would repair the defects and oxide charges in dielectric layers, reducing the quantity of traps in the device, the distinction of flat-band voltage window and current window decreased. Nonetheless, the high-k MIS retained its capacity for utilization in memory applications. Moreover, PMA improved the ideality of electrical characteristics and the stability of device structure, providing a potential and promising process for non-volatile memory device. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93009 |
DOI: | 10.6342/NTU202401606 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
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