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標題: | 碳化矽金氧半結構氧化層製程開發及元件應用之研究 Oxidation Process Development and Device Applications in 4H-SiC MIS Structure |
作者: | 廖威騏 Wei-Chi Liao |
指導教授: | 胡振國 Jenn-Gwo Hwu |
關鍵字: | 碳化矽,金氧半元件,氧化層成長,介面缺陷密度,紫外光感測器,氧化鋁堆疊,記憶體, 4H-SiC,Metal-insulator-semiconductor (MIS),Oxidation processes,Interface trap density,UV sensor,Al2O3 stacking,Memory, |
出版年 : | 2024 |
學位: | 碩士 |
摘要: | 本篇論文重點為探討兩種不同在碳化矽基板上成長氧化層的新穎製程方法,透過材料及電性分析探討氧化層及碳化矽介面處的缺陷密度以及其對於電容-電壓和電流-電壓特性的影響,並探究將金屬/二氧化矽/碳化矽與金屬/氧化鋁/二氧化矽/碳化矽兩種結構的半導體元件分別應用於紫外光感測器以及記憶體之表現。本論文首先介紹一種利用爐管在低於1000 °C的間歇噴濺水合氧化法的創新製程,其在一小時內可成長出約3到7奈米厚的二氧化矽層,並且藉由電導方法得出在平能帶處之介面缺陷密度可低至2 × 10^11 cm^-2eV^-1,與其他前人的研究相比幾乎是最低值。此外,利用此法製造之碳化矽金氧半元件於常溫下偏壓在-6 V,發現其在紫外光照射下之光電流與暗電流相比可高出超過三個數量級,並且在不同功率的紫外光下之光電流展現出高度線性相關性。此元件在從常溫到100 °C高溫下的紫外光感測性能也表現出極佳的可靠度。另一種氧化層製程方法是在常溫下於純水中將碳化矽晶圓透過陽極氧化的技術成長出一層極薄的二氧化矽,再利用熱蒸鍍薄鋁結合陽極氧化的方式形成高介電常數之氧化鋁絕緣層,發現其於平能帶處之介面缺陷密度更可低至1 × 10^11 cm^-2eV^-1。透過氧化鋁層的堆疊,碳化矽金氧半元件的閘極漏電流可在不降低閘極電容的同時被有效的抑制。此外,氧化鋁與二氧化矽介面處的陷阱可做為電荷儲存之用,使得其電容-電壓特性展現出很大的遲滯現象,此特性可做為記憶體之應用。在記憶體的可靠度測試中,發現在100次讀寫操作循環下仍依舊保持穩定的狀態’0’及狀態’1’電容,顯示其具有做為與碳化矽積體電路整合的記憶體元件之潛力。本篇論文於碳化矽氧化層製程方法之研究有突破創新,相信在碳化矽元件的發展及應用上有其重要性。 The purpose of this thesis is to investigate two novel fabrication methods for growing oxide layers on a 4H-SiC substrate. The defect density at the SiO2 / 4H-SiC interface, the C-V and the I-V characteristics, and the performance of semiconductor devices with structures of Al/SiO2/4H-SiC and Al/Al2O3/SiO2/4H-SiC, in applications of UV sensors and memory devices are studied. Firstly, this thesis introduces an innovative fabrication process using intermittent spray hydrated oxidation (ISHO) in a furnace at a temperature below 1000 °C, which is capable of growing about 3 nm to 7 nm of SiO2 within one hour. The interface trap density (D_it) at the flat band voltage is found to be as low as 2 × 10^11 cm^-2eV^-1, which is one of the lowest values in the existing literatures. Additionally, the 4H-SiC metal-insulator-semiconductor (MIS) devices fabricated using this method demonstrate outstanding UV sensing capabilities, with demonstrated photocurrent windows extending over three orders of magnitude in amplification and having linear responsivity, as well as maintaining a photo-to-dark current ratio (PDCR) of about two to three orders of magnitude even at high temperatures up to 100 °C. The other process involves growing a thin SiO2 layer on the 4H-SiC wafers through anodic oxidation (ANO) in DI water at room temperature, followed by thermal evaporation of thin aluminum layers and the ANO technique to form high-κ Al2O3 insulating layers. This yields an even lower D_it of 1 × 10^11 cm^-2eV^-1 at the flat band voltage. With stacking of the Al2O3 layer, the gate leakage current in the 4H-SiC MIS devices is effectively suppressed without notably degrading the gate capacitance. Furthermore, the traps at the Al2O3 / SiO2 interface can be utilized for charge storage purposes. These traps result in significant hysteresis phenomenon in the C-V characteristics, which is suitable for memory applications. In the memory endurance test, the capacitances of the state ‘0’ and the state ‘1’ remained stable through 100 read-write cycles operation, demonstrating the potential for integration as embedded memory with silicon carbide ICs. This thesis presents breakthrough innovations in the fabrication of the oxide layer in silicon carbide devices, highlighting its significance in the development and applications of silicon carbide devices. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93008 |
DOI: | 10.6342/NTU202401607 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
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