具高電源電壓抑制比及高輸出電流的低壓差穩壓器設計與分析

Abstract

線性穩壓器的功能是提供一個精確且沒雜訊的電壓源，通常接在直流電壓轉換器後端，透過內部的回授系統使其輸出能對輸出負載的改變做出快速的回應。線性穩壓器擁有高電源電壓抑制比，然而傳統的線性穩壓器在1MHz~100MHz頻段的雜訊抑制能力往往不及低頻段，在面對高頻信號敏感的電路(例如:ADC)時，需要做些改良。 本論文提出了一種利用前饋電路加上緩衝電路組成的回授技術，並改善線性穩壓器以往在高頻時電源電壓抑制比較差的現象。提出的線性穩壓器輸出電容為4.7μF，然而當輸出電流變大時較大的輸出電容會使線性穩壓器面臨穩定度問題，此回授技術透過把低頻極點分裂成兩個高頻極點的方式改善了穩定度。實驗節果，此線性穩壓器在輸出電流為250毫安培時有高達86度的相位裕度，電源電壓抑制比在10MHz時也有高達-86db。為了滿足不同電子產品的需求，藉由此技術能讓負載電流上升至250毫安培還能保持輸出電壓的精準。 本論文所提出的封包電源轉換器採用TSMC 0.18μm技術的IC中實現。根據測量結果，提出的線性轉換器在輸出電流250毫安培時，有86的相位裕度。電壓抑制比在10MHz時由於量測儀器會有高頻雜訊的干擾只有-35dB。 關鍵詞—前饋電路，電源轉換器，電源電壓抑制比，線性穩壓器

The function of a linear regulator is to provide a precise and noise-free voltage source. It is usually connected to the output of a DC-DC converter. The internal feedback system enables the output of the linear regulator to respond quickly to changes in the output load. While linear regulators have a high-power supply rejection ratio (PSR), traditional low-dropout regulators (LDO) often have limited noise suppression capability in the frequency range of 1MHz to 100MHz, particularly when dealing with circuits sensitive to high-frequency signals such as ADCs. Therefore, improvements are necessary. This paper proposes a feedback technique that combines a feed-forward circuit with a buffer circuit to enhance the voltage suppression ratio of linear regulators at high frequencies. The proposed LDO has an output capacitance of 4.7μF. However, as the output current increases, a larger output capacitance can introduce stability issues. This feedback technique improves stability by splitting the low-frequency pole into two high-frequency poles. In experimental tests, the linear regulator achieved a phase margin of up to 86 degrees at an output current of 250 mA and a PSR of up to -86 dB at 10MHz. This technology allows for accurate output voltage maintenance even when the load current rises to 250 mA, meeting the requirements of various electronic products. The proposed package power converter in this paper is implemented using TSMC 0.18μm IC technology to fulfill its design. The measurement result shows the proposed LDO exhibits a phase margin of 86 degrees at an output current of 250mA. However, the PSR at 10MHz is only -35dB due to interference from high-frequency noise introduced by the measurement instrument. Index Terms—power supply rejection ratio, DC-DC converter, flipped voltage follower, linear voltage regulator.