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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91557完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳景然 | zh_TW |
| dc.contributor.advisor | Ching-Jan Chen | en |
| dc.contributor.author | 黃柏堤 | zh_TW |
| dc.contributor.author | Po-Ti Huang | en |
| dc.date.accessioned | 2024-01-28T16:31:28Z | - |
| dc.date.available | 2024-02-24 | - |
| dc.date.copyright | 2024-01-28 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-08-02 | - |
| dc.identifier.citation | [1] J. Guo and K. N. Leung, "A 25mA CMOS LDO with −85dB PSR at 2.5MHz," 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, 2013, pp. 381-384, doi: 10.1109/ASSCC.2013.6691062.
[2] G. Cai, Y. Lu, C. Zhan and R. P. Martins, "A Fully Integrated FVF LDO With Enhanced Full-Spectrum Power Supply Rejection," in IEEE Transactions on Power Electronics, vol. 36, no. 4, pp. 4326-4337, April 2021, doi: 10.1109/TPEL.2020.3024595. [3] A. P. Patel and G. A. Rincón-Mora, "High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 11, pp. 868-873, Nov. 2010, doi: 10.1109/TCSII.2010.2068110. [4] X. Ming, Q. Li, Z. -k. Zhou and B. Zhang, "An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 1, pp. 40-44, Jan. 2012, doi: 10.1109/TCSII.2011.2177698. [5] M. Al-Shyoukh, H. Lee and R. Perez, "A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation," in IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1732-1742, Aug. 2007, doi: 10.1109/JSSC.2007.900281. [6] K. N. Leung and Y. S. Ng, "A CMOS Low-Dropout Regulator With a Momentarily Current-Boosting Voltage Buffer," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 9, pp. 2312-2319, Sept. 2010, doi: 10.1109/TCSI.2010.2043171. [7] Y. -S. Yuk, S. Jung, C. Kim, H. -D. Gwon, S. Choi and G. -H. Cho, "PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp. 2181-2191, Oct. 2014, doi: 10.1109/TVLSI.2013.2287282. [8] A. Nakhlestani, S. V. Kaveri, M. Radfar and A. Desai, "Low-Power Area-Efficient LDO With Loop-Gain and Bandwidth Enhancement Using Non-Dominant Pole Movement Technique for IoT Applications," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 2, pp. 692-696, Feb. 2021, doi: 10.1109/TCSII.2020.3013646. [9] R. Li, X. Zhang, Y. Zeng, Y. Lin, J. Yang and H. -Z. Tan, "High PSR output-capacitor-less LDO with double buffers technique," 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Glasgow, UK, 2020, pp. 1-4, doi: 10.1109/ICECS49266.2020.9294966. [10] M. El-Nozahi, A. Amer, J. Torres, K. Entesari and E. Sanchez-Sinencio, "High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique," in IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 565-577, March 2010, doi: 10.1109/JSSC.2009.2039685. [11] J.-S. Paek et al., “An 88%-efficiency supply modulator achieving 1.08μs/V fast transition and 100MHz envelope-tracking bandwidth for 5G new radio RF power amplifier,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 358–359, Feb. 2019. [12] D. Arbet, M. Kováč, D. Maljar, L. Nagy and V. Stopjaková, "High Power Supply Rejection LDO Regulator for Switching Applications," 2022 45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), Opatija, Croatia, 2022, pp. 162-167, doi: 10.23919/MIPRO55190.2022.9803648. [13] E. Barteselli, L. Sant, R. Gaggl and A. Baschirotto, "High Audio Band PSR and Fast Settling-Time Dual-Loop LDO Regulator Architecture for Low-Power Application," 2021 International Conference on Electrical, Computer and Energy Technologies (ICECET), Cape Town, South Africa, 2021, pp. 1-4, doi: 10.1109/ICECET52533.2021.9698752. [14] J. Jiang, W. Shu and J. S. Chang, "A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSR Over 10-MHz Frequency Range and 100-mA Load Current Range," in IEEE Journal of Solid-State Circuits, vol. 53, no. 8, pp. 2331-2342, Aug. 2018, doi: 10.1109/JSSC.2018.2837044. [15] F. Lavalle-Aviles, J. Torres and E. Sánchez-Sinencio, "A High Power Supply Rejection and Fast Settling Time Capacitor-Less LDO," in IEEE Transactions on Power Electronics, vol. 34, no. 1, pp. 474-484, Jan. 2019, doi: 10.1109/TPEL.2018.2826922. [16] X. Liu, H. Zhang, P. K. T. Mok and H. C. Luong, "A multi-loop controlled AC-coupling supply modulator with a mode switching CMOS PA in an EER system with envelope shaping," IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1553-1563, June 2019. [17] L. Wang, W. Mao, C. Wu, A. Chang and Y. Lian, "A fast transient LDO based on dual loop FVF with high PSR," 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea (South), 2016, pp. 99-102, doi: 10.1109/APCCAS.2016.7803906. [18] W. -C. Chen, T. -C. Huang, C. -C. Chiu, C. -W. Chang and K. -C. Hsu, "94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 436-438, doi: 10.1109/ISSCC.2018.8310371. [19] M. Khan and M. H. Chowdhury, "Capacitor-less Low-Dropout Regulator (LDO) with Improved PSR and Enhanced Slew-Rate," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-5, doi: 10.1109/ISCAS.2018.8351039. [20] M. Nasrollahpour, S. Hamedi-Hagh, Y. Bastan and P. Amiri, "ECP technique based capacitor-less LDO with high PSR at low frequencies, −89dB PSR at 1MHz and enhanced transient response," 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Giardini Naxos, Italy, 2017, pp. 1-4, doi: 10.1109/SMACD.2017.7981570. [21] Ka Nang Leung, P. K. T. Mok and Wing Hung Ki, "Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design," 1999 IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, FL, USA, 1999, pp. 616-619 vol.2, doi: 10.1109/ISCAS.1999.780838. [22] R. Zhang, Z. Liu and X. Wang, "A Capacitor-less LDO with Nested Miller Compensation and Bulk-Driven Techniques in 90nm CMOS," 2021 4th International Conference on Circuits, Systems and Simulation (ICCSS), Kuala Lumpur, Malaysia, 2021, pp. 51-55, doi: 10.1109/ICCSS51193.2021.9464211. [23] X. L. Tan, S. S. Chong, P. K. Chan and U. Dasgupta, "A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF–10 nF Capacitive Load," in IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2658-2672, Nov. 2014, doi: 10.1109/JSSC.2014.2346762. [24] Y. Zeng, C. -H. Chan, Y. Zhu and R. P. Martins, "An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 2660-2664, doi: 10.1109/ISCAS48785.2022.9937923. [25] C. R. Hipolito, A. Silverio and R. Nuestro, "High PSR LDO with Adaptive-EFFRC for Wearable Biomedical Application," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401677. [26] L. Chen, Q. Cheng, J. Guo and M. Chen, "High-PSR CMOS LDO with embedded ripple feedforward and energy-efficient bandwidth extension," 2015 28th IEEE International System-on-Chip Conference (SOCC), Beijing, China, 2015, pp. 384-389, doi: 10.1109/SOCC.2015.7406988. [27] Y. Zhang, N. Yu, Z. Jiang and Y. Wu, "Output-Capacitor-Less LDO with High PSR," 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Xi'an, China, 2019, pp. 1-3, doi: 10.1109/EDSSC.2019.8754483. [28] J. Yin, S. Huang, Q. Duan and Y. Cheng, "An 800 mA load current LDO with wide input voltage range," 2017 International Conference on Circuits, Devices and Systems (ICCDS), Chengdu, China, 2017, pp. 174-178, doi: 10.1109/ICCDS.2017.8120473. [29] 1A, Low Noise, Ultra High PSR, Low-Dropout Linear Regulator R2519 RICHTEK [30] B. Yang, B. Drost, S. Rao and P. K. Hanumolu, "A high-PSR LDO using a feedforward supply-noise cancellation technique," 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2011, pp. 1-4, doi: 10.1109/CICC.2011.6055409. [31] RT2519 Datasheet ,RICHTEK | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91557 | - |
| dc.description.abstract | 線性穩壓器的功能是提供一個精確且沒雜訊的電壓源，通常接在直流電壓轉換器後端，透過內部的回授系統使其輸出能對輸出負載的改變做出快速的回應。線性穩壓器擁有高電源電壓抑制比，然而傳統的線性穩壓器在1MHz~100MHz頻段的雜訊抑制能力往往不及低頻段，在面對高頻信號敏感的電路(例如:ADC)時，需要做些改良。
本論文提出了一種利用前饋電路加上緩衝電路組成的回授技術，並改善線性穩壓器以往在高頻時電源電壓抑制比較差的現象。提出的線性穩壓器輸出電容為4.7μF，然而當輸出電流變大時較大的輸出電容會使線性穩壓器面臨穩定度問題，此回授技術透過把低頻極點分裂成兩個高頻極點的方式改善了穩定度。實驗節果，此線性穩壓器在輸出電流為250毫安培時有高達86度的相位裕度，電源電壓抑制比在10MHz時也有高達-86db。為了滿足不同電子產品的需求，藉由此技術能讓負載電流上升至250毫安培還能保持輸出電壓的精準。 本論文所提出的封包電源轉換器採用TSMC 0.18μm技術的IC中實現。根據測量結果，提出的線性轉換器在輸出電流250毫安培時，有86的相位裕度。電壓抑制比在10MHz時由於量測儀器會有高頻雜訊的干擾只有-35dB。 關鍵詞—前饋電路，電源轉換器，電源電壓抑制比，線性穩壓器 | zh_TW |
| dc.description.abstract | The function of a linear regulator is to provide a precise and noise-free voltage source. It is usually connected to the output of a DC-DC converter. The internal feedback system enables the output of the linear regulator to respond quickly to changes in the output load. While linear regulators have a high-power supply rejection ratio (PSR), traditional low-dropout regulators (LDO) often have limited noise suppression capability in the frequency range of 1MHz to 100MHz, particularly when dealing with circuits sensitive to high-frequency signals such as ADCs. Therefore, improvements are necessary.
This paper proposes a feedback technique that combines a feed-forward circuit with a buffer circuit to enhance the voltage suppression ratio of linear regulators at high frequencies. The proposed LDO has an output capacitance of 4.7μF. However, as the output current increases, a larger output capacitance can introduce stability issues. This feedback technique improves stability by splitting the low-frequency pole into two high-frequency poles. In experimental tests, the linear regulator achieved a phase margin of up to 86 degrees at an output current of 250 mA and a PSR of up to -86 dB at 10MHz. This technology allows for accurate output voltage maintenance even when the load current rises to 250 mA, meeting the requirements of various electronic products. The proposed package power converter in this paper is implemented using TSMC 0.18μm IC technology to fulfill its design. The measurement result shows the proposed LDO exhibits a phase margin of 86 degrees at an output current of 250mA. However, the PSR at 10MHz is only -35dB due to interference from high-frequency noise introduced by the measurement instrument. Index Terms—power supply rejection ratio, DC-DC converter, flipped voltage follower, linear voltage regulator. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-01-28T16:31:28Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-01-28T16:31:28Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 I
中文摘要 II Abstract III Table of Contents IV List of Figure VII List of Tables IX Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Motivation 2 1.3 Thesis Outline 3 Chapter 2 Structure and application of Low Dropout Linear Regulator (LDO) 4 2.1 Structure and application of LDO 4 2.2 Specification and proper nouns of LDO 5 2.2.1 Dropout Voltage 5 2.2.2 Load Regulation. 6 2.2.3 Line Regulation 7 2.2.4 Transient Response. 8 2.2.5 Quiescent Current 9 2.2.6 Efficiency. 10 2.2.7 Power Supply Rejection 10 2.2.8 Ouput Noise. 11 2.2.9 Voltage Accuracy 12 2.3 Design considerations for an LDO 13 2.3.1 Comparison of Pass Transistors for LDO Linear Regulators 13 2.3.2 Frequency response and Stability analysis of LDO. 15 2.3.3 Power Supply Rejection of LDO 23 2.4 Paper Review 30 Chapter 3 Proposed Low-Dropout Regulator with High PSR and Stability 37 3.1 Proposed LDO Schematic 37 3.1.1 Buffer Design 39 3.1.2 Error Amplifier. 41 3.1.3 Feedforward Feedback circuit 44 3.2 Small Signal Model Analysis for Proposed LDO 49 3.2.1 Loop Gain and Stability of the Proposed LDO 49 3.2.2 PSR analysis of Proposed LDO 52 3.3 Simulation 53 3.3.1 Simulation of the internal feedback 54 3.3.2 Simulation of the LDO linear regulator. 57 3.4 Performance of Proposed LDO Regulator 68 Chapter 4 Measurement Results and Conclusions 71 4.1 Measurement Methods 72 4.2 Measurement Results 74 4.2.1 Measurement Results of transient response 74 4.2.2 Measurement Results of loop gain 76 4.3 Conclusions 81 4.4 Future Works 82 | - |
| dc.language.iso | en | - |
| dc.subject | 電源電壓抑制比 | zh_TW |
| dc.subject | 線性穩壓器 | zh_TW |
| dc.subject | 前饋電路 | zh_TW |
| dc.subject | 電源轉換器 | zh_TW |
| dc.subject | flipped voltage follower | en |
| dc.subject | power supply rejection ratio | en |
| dc.subject | linear voltage regulator | en |
| dc.subject | DC-DC converter | en |
| dc.title | 具高電源電壓抑制比及高輸出電流的低壓差穩壓器設計與分析 | zh_TW |
| dc.title | Design and Analysis of A High Power Supply Rejection Ratio Low-Dropout Regulator with High Output Current | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 林景源;陳耀銘 | zh_TW |
| dc.contributor.oralexamcommittee | Jing-Yuan Lin;Yaow-Ming Chen | en |
| dc.subject.keyword | 電源電壓抑制比,線性穩壓器,前饋電路,電源轉換器, | zh_TW |
| dc.subject.keyword | power supply rejection ratio,DC-DC converter,flipped voltage follower,linear voltage regulator, | en |
| dc.relation.page | 86 | - |
| dc.identifier.doi | 10.6342/NTU202302442 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2023-08-07 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2028-08-01 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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