石墨烯於半導體後端製程的應用

Abstract

隨著半導體製程技術的不斷進步，我們面臨著越來越多的技術挑戰。其中當半導體後端(BEOL)互連導線進行微縮時，它引發了一連串的技術問題。這些問題包括電阻率的增加而導致的元件功耗增加，以及電流密度的增加而引發的電致遷移問題，這些都進一步縮短了互連的壽命。為了克服這些挑戰，本研究提出了兩大方向。

首先，我們使用低溫成長技術在金屬導線上形成石墨烯層，以利用其獨特的特性來降低金屬互連的電阻。實驗結果證明，石墨烯的覆蓋不僅可以降低金屬互連的電阻，還可以提高其能承受的最大電流密度。此外，石墨烯的覆蓋還增強了金屬互連的表面活化能，從而延長了其電致遷移的壽命。

第二個方向考慮了使用多層石墨烯來替代傳統的金屬互連。多層石墨烯的獨特特性使其免受到導線微縮導致電阻率增加的影響，因此被視為半導體後端互連的理想材料。然而，製造高品質的多層石墨烯仍然是一個挑戰。為此，我們提出了一種新方法，能夠迅速生長高品質的石墨烯，並能夠精確地控制其層數。結合插層技術，我們成功地降低了多層石墨烯的片電阻，使其電阻率接近於銅。這為多層石墨烯替代傳統的金屬互連帶來了重大突破。此外，要將其實際應用於半導體後端製程，金屬與石墨烯互連的接觸電阻至關重要，因此我們深入研究了如何降低金屬與石墨烯互連的接觸電阻，並提出了幾種有效的方法。在研究的最後部分，我們還結合了其他過渡金屬二硫化物來製造范德瓦電晶體，並成功證實了透過范德瓦接觸可以解決釘扎效應的問題。

With the continuous evolution of semiconductor fabrication technology, we are confronted with a growing array of technical challenges. As semiconductor back end of line (BEOL) interconnects undergo miniaturization, a cascade of technical issues arises. These challenges include increased component power consumption due to rising resistance and electromigration issues stemming from increased current density, both of which shorten the lifespan of interconnects. To address these challenges, this study proposes two major directions. Firstly, we employ low-temperature growth techniques to form graphene layers on metal interconnects, leveraging its unique properties to reduce the resistance of metal interconnects. Experimental results demonstrate that graphene coverage not only reduces the resistance of metal interconnects but also enhances their ability to withstand higher current densities. Furthermore, graphene coverage strengthens the surface activation energy of metal interconnects, thereby extending their electromigration lifespan. The second direction considers the use of multilayer graphene to replace traditional metal interconnects. The unique characteristics of multilayer graphene make it resistant to the increase in conductivity that typically occurs when wires are scaled down in size. Therefore, it is considered an ideal material for semiconductor back-end interconnects. However, manufacturing high-quality multilayer graphene remains a challenge. To address this, we propose a new method for rapid growth of high-quality graphene while maintaining precise control over its layer count. By incorporating intercalation techniques, we have successfully reduced the sheet resistance of multilayer graphene, making its resistivity comparable to that of copper. This breakthrough paves the way for the substitution of multilayer graphene for traditional metal interconnects. Furthermore, to apply multilayer graphene practically in semiconductor back-end processes, minimizing the contact resistance between metal and graphene interconnects is crucial. Consequently, we have conducted in-depth research on various effective methods for reducing contact resistance between metal and graphene interconnects. In the final part of our study, we combine other transition metal dichalcogenides to create van der Waals heterostructures and have successfully demonstrated that van der Waals contacts can mitigate the pinning effect, addressing a critical issue in this context.