請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91248完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳志毅 | zh_TW |
| dc.contributor.advisor | Chih-I Wu | en |
| dc.contributor.author | 黃健治 | zh_TW |
| dc.contributor.author | Jian-Zhi Huang | en |
| dc.date.accessioned | 2023-12-12T16:23:45Z | - |
| dc.date.available | 2023-12-13 | - |
| dc.date.copyright | 2023-12-12 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-10-05 | - |
| dc.identifier.citation | Reference
[1] A. Mallikarjunan, S. Sharma, and S. Murarka, "Resistivity of copper films at thicknesses near the mean free path of electrons in copper minimization of the diffuse scattering in copper," Electrochemical and Solid-State Letters, vol. 3, no. 9, p. 437, 2000. [2] P. Kapur, J. P. McVittie, and K. C. Saraswat, "Technology and reliability constrained future copper interconnects. I. Resistance modeling," IEEE Transactions on Electron Devices, vol. 49, no. 4, pp. 590-597, 2002. [3] W. Wu and K. Maex, "Studies on size effect of copper interconnect lines," in 2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No. 01EX443), 2001, vol. 1: IEEE, pp. 416-418. [4] G. Lopez, J. Davis, and J. Meindl, "A new physical model and experimental measurements of copper interconnect resistivity considering size effects and line-edge roughness (LER)," in 2009 IEEE international interconnect technology conference, 2009: IEEE, pp. 231-234. [5] D. Gall, A. Jog, and T. Zhou, "Narrow interconnects: The most conductive metals," in 2020 IEEE International Electron Devices Meeting (IEDM), 2020: IEEE, pp. 32.3. 1-32.3. 4. [6] K. Croes et al., "Interconnect metals beyond copper: Reliability challenges and opportunities," in 2018 IEEE International Electron Devices Meeting (IEDM), 2018: IEEE, pp. 5.3. 1-5.3. 4. [7] K. H. Koo, The Comparison Study of Future On-chip Interconnects for High Performance VLSI Applications. Stanford University, 2011. [8] B. Li, T. D. Sullivan, T. C. Lee, and D. Badami, "Reliability challenges for copper interconnects," Microelectronics reliability, vol. 44, no. 3, pp. 365-380, 2004. [9] J. Gambino et al., "Self-aligned metal capping layers for copper interconnects using electroless plating," Microelectronic engineering, vol. 83, no. 11-12, pp. 2059-2067, 2006. [10] E. Zschech et al., "Effect of interface modification on EM-induced degradation mechanisms in copper interconnects," Thin Solid Films, vol. 504, no. 1-2, pp. 279-283, 2006. [11] C. Christiansen et al., "Electromigration-resistance enhancement with CoWP or CuMn for advanced Cu interconnects," in 2011 International Reliability Physics Symposium, 2011: IEEE, pp. 3E. 3.1-3E. 3.5. [12] C.-K. Hu et al., "Reduced Cu interface diffusion by CoWP surface coating," Microelectronic Engineering, vol. 70, no. 2-4, pp. 406-411, 2003. [13] A. C. Neto, F. Guinea, N. M. Peres, K. S. Novoselov, and A. K. Geim, "The electronic properties of graphene," Reviews of modern physics, vol. 81, no. 1, p. 109, 2009. [14] J. Hass, W. De Heer, and E. Conrad, "The growth and morphology of epitaxial multilayer graphene," Journal of Physics: Condensed Matter, vol. 20, no. 32, p. 323202, 2008. [15] Y. Zhang, L. Zhang, and C. Zhou, "Review of chemical vapor deposition of graphene and related applications," Accounts of chemical research, vol. 46, no. 10, pp. 2329-2339, 2013. [16] G.-H. Lee et al., "High-strength chemical-vapor–deposited graphene and grain boundaries," science, vol. 340, no. 6136, pp. 1073-1076, 2013. [17] A. Pirkle et al., "The effect of chemical residues on the physical and electrical properties of chemical vapor deposited graphene transferred to SiO2," Applied Physics Letters, vol. 99, no. 12, 2011. [18] C. Mattevi, H. Kim, and M. Chhowalla, "A review of chemical vapour deposition of graphene on copper," Journal of Materials Chemistry, vol. 21, no. 10, pp. 3324-3334, 2011. [19] R. Kato, S. Minami, Y. Koga, and M. Hasegawa, "High growth rate chemical vapor deposition of graphene under low pressure by RF plasma assistance," Carbon, vol. 96, pp. 1008-1013, 2016. [20] S.-H. Chan, S.-H. Chen, W.-T. Lin, M.-C. Li, Y.-C. Lin, and C.-C. Kuo, "Low-temperature synthesis of graphene on Cu using plasma-assisted thermal chemical vapor deposition," Nanoscale research letters, vol. 8, pp. 1-5, 2013. [21] R. Muñoz, C. Munuera, J. I. Martínez, J. Azpeitia, C. Gómez-Aleixandre, and M. García-Hernández, "Low temperature metal free growth of graphene on insulating substrates by plasma assisted chemical vapor deposition," 2D Materials, vol. 4, no. 1, p. 015009, 2016. [22] P. Zhao et al., "Self-limiting chemical vapor deposition growth of monolayer graphene from ethanol," The Journal of Physical Chemistry C, vol. 117, no. 20, pp. 10755-10763, 2013. [23] X. Li et al., "Large-area synthesis of high-quality and uniform graphene films on copper foils," science, vol. 324, no. 5932, pp. 1312-1314, 2009. [24] R. S. Edwards and K. S. Coleman, "Graphene film growth on polycrystalline metals," Accounts of chemical research, vol. 46, no. 1, pp. 23-30, 2013. [25] M. E. Ramon et al., "CMOS-compatible synthesis of large-area, high-mobility graphene by chemical vapor deposition of acetylene on cobalt thin films," ACS nano, vol. 5, no. 9, pp. 7198-7204, 2011. [26] R. Munoz and C. Gómez‐Aleixandre, "Review of CVD synthesis of graphene," Chemical Vapor Deposition, vol. 19, no. 10-11-12, pp. 297-322, 2013. [27] A. Maffucci and G. Miano, "Electrical properties of graphene for interconnect applications," Applied Sciences, vol. 4, no. 2, pp. 305-317, 2014. [28] A. Hazra and S. Basu, "Graphene nanoribbon as potential on-chip interconnect material—A review," C, vol. 4, no. 3, p. 49, 2018. [29] J. Jiang et al., "Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects," Nano letters, vol. 17, no. 3, pp. 1482-1488, 2017. [30] R. Mehta, S. Chugh, and Z. Chen, "Enhanced electrical and thermal conduction in graphene-encapsulated copper nanowires," Nano letters, vol. 15, no. 3, pp. 2024-2030, 2015. [31] L. Li, Z. Zhu, T. Wang, J. A. Currivan-Incorvia, A. Yoon, and H.-S. P. Wong, "BEOL compatible graphene/Cu with improved electromigration lifetime for future interconnects," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016: IEEE, pp. 9.5. 1-9.5. 4. [1] A. Nag et al., "High-performance poly (benzoxazole/benzimidazole) bio-based plastics with ultra-low dielectric constant from 3-amino-4-hydroxybenzoic acid," Polymer Degradation and Stability, vol. 162, pp. 29-35, 2019. [2] S. Mosca, C. Conti, N. Stone, and P. Matousek, "Spatially offset Raman spectroscopy," Nature Reviews Methods Primers, vol. 1, no. 1, p. 21, 2021. [3] A. C. Ferrari et al., "Raman spectrum of graphene and graphene layers," Physical review letters, vol. 97, no. 18, p. 187401, 2006. [4] I. Childres, L. A. Jauregui, W. Park, H. Cao, and Y. P. Chen, "Raman spectroscopy of graphene and related materials," New developments in photon and materials research, vol. 1, pp. 1-20, 2013. [5] C. Casiraghi et al., "Raman spectroscopy of graphene edges," Nano letters, vol. 9, no. 4, pp. 1433-1441, 2009. [6] L. G. Cançado et al., "Disentangling contributions of point and line defects in the Raman spectra of graphene-related materials," 2D Materials, vol. 4, no. 2, p. 025039, 2017. [7] B. Lv, T. Qian, and H. Ding, "Angle-resolved photoemission spectroscopy and its application to topological materials," Nature Reviews Physics, vol. 1, no. 10, pp. 609-626, 2019. [8] F. Smits, "Measurement of sheet resistivities with the four‐point probe," Bell System Technical Journal, vol. 37, no. 3, pp. 711-718, 1958. [9] J. R. Black, "Electromigration—A brief survey and some recent results," IEEE Transactions on Electron Devices, vol. 16, no. 4, pp. 338-347, 1969. [10] G. Reeves and H. Harrison, "Obtaining the specific contact resistance from transmission line model measurements," IEEE Electron device letters, vol. 3, no. 5, pp. 111-113, 1982. [11] S. Venica et al., "Reliability analysis of the metal-graphene contact resistance extracted by the transfer length method," in 2018 IEEE International Conference on Microelectronic Test Structures (ICMTS), 2018: IEEE, pp. 57-62. [1] C. Tellier, A. Tosser, and C. Boutrit, "The Mayadas-Shatzkes conduction model treated as a Fuchs-Sondheimer model," Thin Solid Films, vol. 44, no. 2, pp. 201-208, 1977. [2] R. Smith et al., "An evaluation of Fuchs-Sondheimer and Mayadas-Shatzkes models below 14nm node wide lines," AIP Advances, vol. 9, no. 2, 2019. [3] R. Mehta, S. Chugh, and Z. Chen, "Enhanced electrical and thermal conduction in graphene-encapsulated copper nanowires," Nano letters, vol. 15, no. 3, pp. 2024-2030, 2015. [4] M. Son et al., "Copper-graphene heterostructure for back-end-of-line compatible high-performance interconnects," npj 2D Materials and Applications, vol. 5, no. 1, p. 41, 2021. [5] L. Li, Z. Zhu, T. Wang, J. A. Currivan-Incorvia, A. Yoon, and H.-S. P. Wong, "BEOL compatible graphene/Cu with improved electromigration lifetime for future interconnects," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016: IEEE, pp. 9.5. 1-9.5. 4. [6] S. Chugh, R. Mehta, N. Lu, F. D. Dios, M. J. Kim, and Z. Chen, "Comparison of graphene growth on arbitrary non-catalytic substrates using low-temperature PECVD," Carbon, vol. 93, pp. 393-399, 2015. [7] Z. Ullah et al., "A comparative study of graphene growth by APCVD, LPCVD and PECVD," Materials Research Express, vol. 5, no. 3, p. 035606, 2018. [8] Z. Li et al., "Low-temperature growth of graphene by chemical vapor deposition using solid and liquid carbon sources," ACS nano, vol. 5, no. 4, pp. 3385-3390, 2011. [9] J.-b. Wang et al., "A review of graphene synthesisatlow temperatures by CVD methods," New Carbon Materials, vol. 35, no. 3, pp. 193-208, 2020. [10] Y. Yan et al., "Synthesis of graphene: Potential carbon precursors and approaches," Nanotechnology Reviews, vol. 9, no. 1, pp. 1284-1314, 2020. [11] C.-M. Sung and M.-F. Tai, "Reactivities of transition metals with carbon: Implications to the mechanism of diamond synthesis under high pressure," International Journal of Refractory Metals and Hard Materials, vol. 15, no. 4, pp. 237-256, 1997. [1] S. Dutta, K. Moors, M. Vandemaele, and C. Adelmann, "Finite size effects in highly scaled ruthenium interconnects," IEEE Electron Device Letters, vol. 39, no. 2, pp. 268-271, 2018. [2] G. Bonilla, N. Lanzillo, C.-K. Hu, C. Penny, and A. Kumar, "Interconnect scaling challenges, and opportunities to enable system-level performance beyond 30 nm pitch," in 2020 IEEE International Electron Devices Meeting (IEDM), 2020: IEEE, pp. 20.4. 1-20.4. 4. [3] K. Zhao, Y. Hu, G. Du, Y. Zhao, and J. Dong, "Mechanisms of Scaling Effect for Emerging Nanoscale Interconnect Materials," Nanomaterials, vol. 12, no. 10, p. 1760, 2022. [4] X. Lin and D. Pramanik, "Future interconnect technologies and copper metallization," Solid State Technology, vol. 41, no. 10, pp. 63-70, 1998. [5] C.-C. Yang, S. Cohen, T. Shaw, P.-C. Wang, T. Nogami, and D. Edelstein, "Characterization of “Ultrathin-Cu”/Ru (Ta)/TaN liner stack for copper interconnects," IEEE Electron Device Letters, vol. 31, no. 7, pp. 722-724, 2010. [6] S.-Y. Yang et al., "Ultra-thin ALD-MnN barrier for low resistance advanced interconnect technology," in 2017 IEEE International Interconnect Technology Conference (IITC), 2017: IEEE, pp. 1-3. [7] Y. Kotsugi et al., "Atomic layer deposition of Ru for replacing Cu-interconnects," Chemistry of Materials, vol. 33, no. 14, pp. 5639-5651, 2021. [8] J. Jiang et al., "Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects," Nano letters, vol. 17, no. 3, pp. 1482-1488, 2017. [9] J. Jiang, J. H. Chu, and K. Banerjee, "CMOS-compatible doped-multilayer-graphene interconnects for next-generation VLSI," in 2018 IEEE International Electron Devices Meeting (IEDM), 2018: IEEE, pp. 34.5. 1-34.5. 4. [10] N. C. Wang, S. Sinha, B. Cline, C. D. English, G. Yeric, and E. Pop, "Replacing copper interconnects with graphene at a 7-nm node," in 2017 IEEE International Interconnect Technology Conference (IITC), 2017: IEEE, pp. 1-3. [11] C. J. An et al., "Ultraclean transfer of CVD-grown graphene and its application to flexible organic photovoltaic cells," Journal of Materials Chemistry A, vol. 2, no. 48, pp. 20474-20480, 2014. [12] P. Guerrier, K. K. Nielsen, and J. H. Hattel, "Temperature dependence and magnetic properties of injection molding tool materials used in induction heating," IEEE Transactions on magnetics, vol. 51, no. 9, pp. 1-7, 2015. [13] J. M. Asensio et al., "To heat or not to heat: a study of the performances of iron carbide nanoparticles in magnetic heating," Nanoscale, vol. 11, no. 12, pp. 5402-5411, 2019. [14] Z. Yan, Z. Zhuxia, L. Tianbao, L. Xuguang, and X. Bingshe, "XPS and XRD study of FeCl3–graphite intercalation compounds prepared by arc discharge in aqueous solution," Spectrochimica Acta Part A: Molecular and Biomolecular Spectroscopy, vol. 70, no. 5, pp. 1060-1064, 2008. [15] W. Zhao, P. H. Tan, J. Liu, and A. C. Ferrari, "Intercalation of few-layer graphite flakes with FeCl3: Raman determination of Fermi level, layer by layer decoupling, and stability," Journal of the American Chemical Society, vol. 133, no. 15, pp. 5941-5946, 2011. [16] Y. Liu et al., "Approaching the Schottky–Mott limit in van der Waals metal–semiconductor junctions," Nature, vol. 557, no. 7707, pp. 696-700, 2018. [17] Y. Wang et al., "Van der Waals contacts between three-dimensional metals and two-dimensional semiconductors," Nature, vol. 568, no. 7750, pp. 70-74, 2019. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91248 | - |
| dc.description.abstract | 隨著半導體製程技術的不斷進步,我們面臨著越來越多的技術挑戰。其中當半導體後端(BEOL)互連導線進行微縮時,它引發了一連串的技術問題。這些問題包括電阻率的增加而導致的元件功耗增加,以及電流密度的增加而引發的電致遷移問題,這些都進一步縮短了互連的壽命。為了克服這些挑戰,本研究提出了兩大方向。
首先,我們使用低溫成長技術在金屬導線上形成石墨烯層,以利用其獨特的特性來降低金屬互連的電阻。實驗結果證明,石墨烯的覆蓋不僅可以降低金屬互連的電阻,還可以提高其能承受的最大電流密度。此外,石墨烯的覆蓋還增強了金屬互連的表面活化能,從而延長了其電致遷移的壽命。 第二個方向考慮了使用多層石墨烯來替代傳統的金屬互連。多層石墨烯的獨特特性使其免受到導線微縮導致電阻率增加的影響,因此被視為半導體後端互連的理想材料。然而,製造高品質的多層石墨烯仍然是一個挑戰。為此,我們提出了一種新方法,能夠迅速生長高品質的石墨烯,並能夠精確地控制其層數。結合插層技術,我們成功地降低了多層石墨烯的片電阻,使其電阻率接近於銅。這為多層石墨烯替代傳統的金屬互連帶來了重大突破。此外,要將其實際應用於半導體後端製程,金屬與石墨烯互連的接觸電阻至關重要,因此我們深入研究了如何降低金屬與石墨烯互連的接觸電阻,並提出了幾種有效的方法。在研究的最後部分,我們還結合了其他過渡金屬二硫化物來製造范德瓦電晶體,並成功證實了透過范德瓦接觸可以解決釘扎效應的問題。 | zh_TW |
| dc.description.abstract | With the continuous evolution of semiconductor fabrication technology, we are confronted with a growing array of technical challenges. As semiconductor back end of line (BEOL) interconnects undergo miniaturization, a cascade of technical issues arises. These challenges include increased component power consumption due to rising resistance and electromigration issues stemming from increased current density, both of which shorten the lifespan of interconnects. To address these challenges, this study proposes two major directions.
Firstly, we employ low-temperature growth techniques to form graphene layers on metal interconnects, leveraging its unique properties to reduce the resistance of metal interconnects. Experimental results demonstrate that graphene coverage not only reduces the resistance of metal interconnects but also enhances their ability to withstand higher current densities. Furthermore, graphene coverage strengthens the surface activation energy of metal interconnects, thereby extending their electromigration lifespan. The second direction considers the use of multilayer graphene to replace traditional metal interconnects. The unique characteristics of multilayer graphene make it resistant to the increase in conductivity that typically occurs when wires are scaled down in size. Therefore, it is considered an ideal material for semiconductor back-end interconnects. However, manufacturing high-quality multilayer graphene remains a challenge. To address this, we propose a new method for rapid growth of high-quality graphene while maintaining precise control over its layer count. By incorporating intercalation techniques, we have successfully reduced the sheet resistance of multilayer graphene, making its resistivity comparable to that of copper. This breakthrough paves the way for the substitution of multilayer graphene for traditional metal interconnects. Furthermore, to apply multilayer graphene practically in semiconductor back-end processes, minimizing the contact resistance between metal and graphene interconnects is crucial. Consequently, we have conducted in-depth research on various effective methods for reducing contact resistance between metal and graphene interconnects. In the final part of our study, we combine other transition metal dichalcogenides to create van der Waals heterostructures and have successfully demonstrated that van der Waals contacts can mitigate the pinning effect, addressing a critical issue in this context. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-12-12T16:23:45Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-12-12T16:23:45Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Contents
Abstract I 摘要 V Contents VI List of Figures VIII Table of Figures XII Chapter 1. Introduction 1 1-1 Challenges in Semiconductor BEOL Interconnects 3 1-2 Electromigration Effects 6 1-3 Graphene and Multilayer Graphene 8 1-4 Methods of Graphene Growth 11 1-5 Applications of Multilayer Graphene in BEOL Processes 14 1-6. Organization of this Dissertation 17 Reference 18 Chapter 2. Experiments & Methodologies 21 2-1. Preparation of Graphene-Capped Metal Interconnects 21 2-2 Preparation of Multilayer Graphene 25 2-3. Analysis of Material Qualities 26 2-4. Electrical Testing of Metal Interconnects 31 Reference 36 Chapter 3. Improving the Electromigration Life of Advanced Interconnects through Graphene Capping. 37 3-1 Motivation 37 3-2 Growth of Graphene on Metal Films 38 3-3 Growth of Graphene on Metal Interconnect 43 3-4 Conclusion 51 Reference 52 Chapter 4. Intercalated Multilayer Graphene with Ultra Low Resistance for Next-Generation Interconnects 53 4-1 Motivation 53 4-2 Growth of Multilayer Graphene via High-Frequency Heating 57 4-3. Intercalated Graphene 63 4-4 Contact Resistance Between Metal and Graphene 68 4-5 Graphene as Contact Electrodes 71 4-6 Conclusion 75 Reference 76 Chapter 5. Conclusions and future work 78 Chapter 6. Publication list 80 | - |
| dc.language.iso | en | - |
| dc.subject | 互連導線 | zh_TW |
| dc.subject | 范德瓦電晶體 | zh_TW |
| dc.subject | 接觸電阻 | zh_TW |
| dc.subject | 電阻率 | zh_TW |
| dc.subject | 多層石墨烯 | zh_TW |
| dc.subject | 互連導線 | zh_TW |
| dc.subject | 半導體後端製程 | zh_TW |
| dc.subject | 范德瓦電晶體 | zh_TW |
| dc.subject | 接觸電阻 | zh_TW |
| dc.subject | 電阻率 | zh_TW |
| dc.subject | 多層石墨烯 | zh_TW |
| dc.subject | 半導體後端製程 | zh_TW |
| dc.subject | van der Waals contacts FET | en |
| dc.subject | semiconductor back end of line | en |
| dc.subject | interconnects | en |
| dc.subject | multilayer graphene | en |
| dc.subject | resistivity | en |
| dc.subject | contact resistance | en |
| dc.subject | van der Waals contacts FET | en |
| dc.subject | semiconductor back end of line | en |
| dc.subject | interconnects | en |
| dc.subject | multilayer graphene | en |
| dc.subject | resistivity | en |
| dc.subject | contact resistance | en |
| dc.title | 石墨烯於半導體後端製程的應用 | zh_TW |
| dc.title | Application of graphene in the back-end of line interconnects | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-1 | - |
| dc.description.degree | 博士 | - |
| dc.contributor.oralexamcommittee | 吳育任;陳美杏;張子璿;林鴻志 | zh_TW |
| dc.contributor.oralexamcommittee | Yuh-Renn Wu;Mei-Hsin Chen;Tzu-Hsuan Chang;Horng-Chih Lin | en |
| dc.subject.keyword | 半導體後端製程,互連導線,多層石墨烯,電阻率,接觸電阻,范德瓦電晶體, | zh_TW |
| dc.subject.keyword | semiconductor back end of line,interconnects,multilayer graphene,resistivity,contact resistance,van der Waals contacts FET, | en |
| dc.relation.page | 81 | - |
| dc.identifier.doi | 10.6342/NTU202304289 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-10-06 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 光電工程學研究所 | - |
| dc.date.embargo-lift | 2028-10-03 | - |
| 顯示於系所單位: | 光電工程學研究所 | |
文件中的檔案:
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-112-1.pdf 未授權公開取用 | 3.32 MB | Adobe PDF | 檢視/開啟 |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。
