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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/90603Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 陳景然 | zh_TW |
| dc.contributor.advisor | Ching-jan Chen | en |
| dc.contributor.author | 交友識 | zh_TW |
| dc.contributor.author | Giao Huu Thuc | en |
| dc.date.accessioned | 2023-10-03T16:49:15Z | - |
| dc.date.available | 2023-11-10 | - |
| dc.date.copyright | 2023-10-03 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-06-20 | - |
| dc.identifier.citation | [1] Lidow, M. de Rooij, J. Strydom, D. Reusch, and J.Glaser, Gan Transistors for Efficient Power Conversion. Hoboken, NJ, USA: Wiley, 2019.
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Cong and H. Lee, "Design of On-Chip Gate Drivers With Power-Efficient High-Speed Level Shifting and Dynamic Timing Control for High-Voltage Synchronous Switching Power Converters," in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1463-1477, June 2015. [8] C. -J. Chen, P. -K. Chiu, Y. -M. Chen, P. -Y. Wang and Y. -C. Chang, "An Integrated Driver With Adaptive Dead-Time Control for GaN-Based Synchronous Buck Converter," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, pp. 539-543, Feb. 2022. [9] X. Ke and D. Brian Ma, "An Automotive-Use 5MHz, 40V to 1.2V, Single-Stage AOT GaN DC-DC Converter with One-Cycle Transient Response and Load-Adaptive Dead Time Control," in IEEE Applied Power Electronics Conference and Exposition (APEC), Phoenix, AZ, USA, 2021, pp. 513-516. [10] Q. Cheng and H. Lee, "A high-frequency non-isolated ZVS synchronous buck-boost LED driver with fully-integrated dynamic dead-time controlled gate drive," in IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, USA, 2018, pp. 419-422. [11] X. Ke, J. Sankman, M. K. Song, P. Forghani and D. B. Ma, "16.8 A 3-to-40V 10-to-30MHz automotive-use GaN driver with active BST balancing and VSW dual-edge dead-time modulation achieving 8.3% efficiency improvement and 3.4ns constant propagation delay," in IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 302-304. [12] J. Wittmann, A. Barner, T. Rosahl and B. Wicht, "An 18 V Input 10 MHz Buck Converter With 125 ps Mixed-Signal Dead Time Control," in IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1705-1715, July 2016. [13] S. T. Li, P. Y. Wang, C. J. Chen and C. -C. Hsu, "A 10MHz GaN Driver with Gate Ringing Suppression and Active Bootstrap Control," in IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia), 2019, pp. 1-4. [14] B. -D. Choi, "Enhancement of current driving capability in data driver ICs for plasma display panels," in IEEE Transactions on Consumer Electronics, vol. 55, no. 3, pp. 992-997, August 2009. [15] M. Khorasani et al., "Low-power static and dynamic high-voltage CMOS level-shifter circuits," in IEEE International Symposium on Circuits and Systems, Seattle, WA, USA, 2008, pp. 1946-1949. [16] Y. -M. Li, C. -B. Wen, B. Yuan, L. -M. Wen and Q. Ye, "A high speed and power-efficient level shifter for high voltage buck converter drivers," in 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 2010, pp. 309-311. [17] Efficient Power Conversion Corp. AN015-Introducing a Family of eGaN FETs for Multi-Megahertz Hard Switching Applications. Accessed: 2019. [Online]. Available: http://epc-co.com/epc/documents [18] S. T. Li, P. Y. Wang, C. J. Chen and C. -C. Hsu, "A 10MHz GaN Driver with Gate Ringing Suppression and Active Bootstrap Control," in 2019 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia), 2019, pp. 1-4. [19] Phillip E. Allen and Douglas R. Holberg, CMOS Analog circuit design 2nd Edition, Oxford University 2002. [20] D. Johns and K. Martin, Analog integrated circuit design, New York: Wiley, 2000. [21] C. Manoj Kumar, S. Bharath, K. Anusha and C. Ajay Kumar, “Design of a double tail dynamic comparator for low power and high speed applications,” in International Journal of Scientific & Engineering Research, Vol. 7, Issue 3, March-2016. [22] S. Aakash, A. Anisha, G. J. Das, T. Abhiram and J. P. Anita, "Design of a low power, high speed double tail comparator," in International Conference on Circuit, Power, and Computing Technologies (ICCPCT), Kollam, India, 2017, pp. 1-5. [23] H. O. Johansson, "A simple precharged CMOS phase frequency detector," in IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 295-299, Feb. 1998. [24] M. K. Hati and T. K. Bhattacharyya, "A PFD and Charge Pump switching circuit to optimize the output phase noise of the PLL in 0.13-µm CMOS," in International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), Bengaluru, India, 2015, pp. 1-6. [25] Manas Kumar Hati, Tarun Kanti Bhattacharyya, "A high o/p resistance, wide swing and perfect current matching charge pump having switching circuit for PLL", in Microelectronics Journal, Volume 44, Issue 8, 2013, pages 649-657. [26] Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill, New Delhi, 2008. [27] I. A. Young, J. K. Greason, J. E. Smith and K. L. Wong, "A PLL clock generator with 5 to 110 MHz lock range for microprocessors," 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, USA, 1992, pp. 50-51. [28] Liang Dai and R. Harjani, "CMOS switched-op-amp-based sample-and-hold circuit," in IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 109-113, Jan. 2000. [29] Ping-Kun Chiu, Ching-Jan Chen, “A Gate Driver IC with Adaptive Dead-Time Control for GaN-Based Synchronous Buck Converter” Mater thesis, Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan, 2020. [30] D. Liu, S. J. Hollis, H. C. P. Dymond, N. McNeill and B. H. Stark, "Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 7, pp. 688-692, July 2016. [31] J. Delaine, P. -O. Jeannin, D. Frey and K. Guepratte, "High frequency DC-DC converter using GaN device," in Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Orlando, FL, USA, 2012, pp. 1754-1761. [32] M. K. Song, L. Chen, J. Sankman, S. Terry and D. Ma, "16.7 A 20V 8.4W 20MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constant propagation delay and 1ns switching rise time," in IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2015, pp. 1-3. [33] A. Seidel and B. Wicht, "25.3 A 1.3A gate driver for GaN with fully integrated gate charge buffer capacitor delivering 11nC enabled by high-voltage energy storing," in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2017, pp. 432-433. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/90603 | - |
| dc.description.abstract | 本論文提出了一種用於具有雙側自適應死區時間發生器 (DTG) 的基於 GaN 的同步降壓轉換器的柵極驅動器 IC，以提高傳統固定或單側 DTG 的轉換器效率。 所提議的驅動器 IC 包含兩個主要子塊，例如相位誤差檢測器 (PED) 和粗調/精細控制器。 應用邊沿檢測原理，所提出的死區時間控制可以最小化死區時間和開關電壓兩端的反向傳導損耗，Vx，使用 e-mode GaN 器件的 1MHz 12 V 至 5 V 降壓轉換器具有 0.2 至 2 A 負載電流範圍。 設計的 IC 採用 TSMC 0.18 μm HVG2 工藝製造。 根據測量結果，1 A 負載電流下的最小死區時間為 47 ps。 在負載條件 I_load=0.8 A 時，峰值效率達到 94.15%。與 10 ns 固定 DTG 相比，模擬效率提高了約 2.16%。 | zh_TW |
| dc.description.abstract | This thesis proposes a gate driver IC for a GaN-based synchronous buck converter with a double-sided adaptive dead-time generator (DTG) to improve the converter efficiency of conventional fixed or single-sided DTGs. The proposed driver IC contains two main sub-blocks such as the phase error detector (PED) and the coarse/fine controllers. Applying the edge detection principle, the proposed dead-time control can minimize the dead-time and reverse conduction loss on both edges of the switching voltage, Vx, of a 1MHz 12 V to 5 V buck converter using e-mode GaN devices with 0.2 to 2 A load current range. The designed IC is fabricated with TSMC 0.18 μm HVG2 process. According to the measurement results, the minimum dead time at 1 A load current is 47 ps. The peak efficiency achieves 94.15 % at load condition I_load=0.8 A. Compared with a 10 ns fixed DTG, the simulated efficiency is improved by approximate 2.16 %. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-10-03T16:49:15Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-10-03T16:49:15Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Oral examination committee approval letter I
Acknowledgement II Abstract III Table of Contents IV List of Figures VII List of Tables XII Chapter 1 Introduction 1 1.1 Research Background 1 1.2 Thesis Motivation 2 1.3 Thesis Outline 4 Chapter 2 Literature Review of Gate Driver IC for GaN Devices 6 2.1 Overview of GaN Devices 6 2.2 General Analyses and Motivation of Dead-time Control 9 2.3 Review of Level Shifter 14 2.4 Review of Bootstrap Circuit 17 2.5 Summary 20 Chapter 3 Concept of Proposed Gate Driver IC 21 3.1 System Structure of Gate Driver IC 21 3.2 Overall Operation Principle 23 3.3 Phase Error Detector 25 3.4 Concept of Coarse/Fine Controller 27 3.5 Concept of A Double Side Dead-time Generator 29 3. 6 Summary 33 Chapter 4 Circuit Implementation and Functionality 34 4.1 Phase Error Detector 34 4.1.1 Comparator 36 4.2 Course/Fine Controller 43 4.2.1 Coarse Controller 43 4.2.2 Fine Controller 45 4.3 Double-sided Adaptive Dead-time Control 49 4.3.1 Management of Dead-time on Falling Side of Vx 49 4.3.2 Management of Dead-time on Rising Side of Vx 51 4.3.3 Varactor’s Properties and Operations 53 4.3.4 Modelling Dead-time on Falling Side of Vx 55 4.4 Gate Driver 59 4.5 Level Shifter 62 4.6 Active Bootstrap Circuit 63 4.7 Full Transistor-Level Simulation 65 Chapter 5 Measurement Results 70 5.1 Introduction 70 5.2 Printed Circuit Board (PCB) Design and Measurement Setup 74 5.3 Measurement Results 77 Chapter 6 Conclusion and Future Work 89 6.1 Conclusions 89 6.2 Future works 90 References 91 | - |
| dc.language.iso | en | - |
| dc.subject | 相位誤差檢測器。 | zh_TW |
| dc.subject | 柵極驅動器 IC; | zh_TW |
| dc.subject | 自適應死區時間控制; | zh_TW |
| dc.subject | GaN 器件; | zh_TW |
| dc.subject | DC-DC 轉換器; | zh_TW |
| dc.subject | 粗調/微調控制器; | zh_TW |
| dc.subject | DC-DC converter; | en |
| dc.subject | Adaptive dead-time control; | en |
| dc.subject | GaN devices; | en |
| dc.subject | Gate Driver IC; | en |
| dc.subject | Phase Error Detector. | en |
| dc.subject | Coarse/Fine controllers; | en |
| dc.title | 應用於氮化鎵同步降壓轉換器之具雙側自適應死區時間產生 器之閘極驅動器積體電路 | zh_TW |
| dc.title | A Gate Driver IC for GaN-Based Synchronous Buck Converter with A Double-Sided Adaptive Dead-Time Generator | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳柏宏; 金藝璘 | zh_TW |
| dc.contributor.oralexamcommittee | Po-hung Chen;Katherine-a Kim | en |
| dc.subject.keyword | 柵極驅動器 IC;,自適應死區時間控制;,GaN 器件;,DC-DC 轉換器;,粗調/微調控制器;,相位誤差檢測器。, | zh_TW |
| dc.subject.keyword | Gate Driver IC;,Adaptive dead-time control;,GaN devices;,DC-DC converter;,Coarse/Fine controllers;,Phase Error Detector., | en |
| dc.relation.page | 95 | - |
| dc.identifier.doi | 10.6342/NTU202301049 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2023-06-21 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2028-06-30 | - |
| Appears in Collections: | 電子工程學研究所 | |
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| ntu-111-2.pdf Restricted Access | 6.82 MB | Adobe PDF | View/Open |
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