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完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor陳建彰
dc.contributor.authorYi-Shiuan Tsaien
dc.contributor.author蔡宜軒zh_TW
dc.date.accessioned2021-05-20T20:05:57Z-
dc.date.available2016-08-23
dc.date.available2021-05-20T20:05:57Z-
dc.date.copyright2011-08-23
dc.date.issued2011
dc.date.submitted2011-08-15
dc.identifier.citation第一章參考文獻:
[1] Y. Kuo, Thin Film Transistors: Amorphous Silicon Thin Film Transistors, Kluwer Academic Publishers, pp. 2-3, 2004.
[2] C. R. Kagan and P. Andry, Thin-Film Transistors, Marcel Dekker, Inc., pp. 15-18, 2003.
[3] A. J. Snell, W. E. Spear, P. G. Le Comber, and K. Mackenzie, “Application of amorphous silicon field effect transistors in integrated circuits,” Appl. Phys. A, 26, 2, pp. 83-86, 1981.
[4] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-fllm transistors using amorphous oxide semiconductors,” Nature (London), 432, pp. 488-492, 2004.
[5] B. D. Ahn, W. H. Jeong, H. S. Shin, D. L. Kim, H. J. Kim, J. K. Jeong, S. H. Choi, and M. K. Han, “Effect of excimer laser annealing on the performance of amorphous IGZO TFT,” Electrochem. Solid-State Lett., 12, 12, pp. H430-H432, 2009.
[6] H. Kawamoto, “The history of liquid-crystal displays,” Proceedings of the IEEE, 90, 4, pp. 460-500, 2002.
[7] C.-H. Lee, A. Sazonov, and A. Nathan, “High-mobility nanocrystalline silicon thin-film transistors fabricated by plasma-enhanced chemical vapor deposition,” Appl. Phys. Lett., 86, 22, p. 222106, 2005.
[8] A. Z. Kattamis, R. J. Holmes, I-C. Cheng, K. Long, J. C. Sturm, S. R. Forrest, and S. Wagner, “High mobility nanocrystalline silicon transistors on clear plastic substrates,” IEEE Electron Device Lett., 27, 1, pp. 49-51, 2006.
[9] E. M. C. Fortunato, P. M. C. Barquinha, A. C. M. B. G. Pimentel, A. M. F. Gonçalves, A. J. S. Marques, R. F. P. Martins, and L. M.N. Pereira, “Wide-bandgap high-mobility ZnO thin-film transistors produced at room temperature,” Appl. Phys. Lett., 85, 13, pp. 2541-2543, 2004.
[10] Y.-L. Wang, F. Ren, W. Lim, D. P. Norton, S. J. Pearton, I. I. Kravchenko, and J. M. Zavada, “Room temperature deposited indium zinc oxide thin film transistors,” Appl. Phys. Lett., 90, 23, p. 232103, 2007.
[11] M. G. McDowell, R. J. Sanderson, and I. G. Hill, “Combinatorial study of zinc tin oxide thin-film transistors,” Appl. Phys. Lett., 92, 1, p. 013502, 2008.
[12] J.-W. Tsai, C.-Y. Huang, Y.-H. Tai, F.-C. Su, F.-C. Luo, H.-C. Tuan, and H.-C. Cheng “Reducing threshold voltage shifts in amorphous silicon thin film transistors by hydrogenating the gate nitride prior to amorphous silicon deposition,” Appl. Phys. Lett., 71, 9, pp. 1237-1239, 1997.
[13] H. Kavak, C. Gruber, H. Shanks, A. Landin, A. Constant, and S. Burns, “Thin film transistors on polyimide substrates,” J. Non-Cryst. Solids, 266-269, pp. 1325-1328, 2000.
[14] J. B. Choi, D. C. Yun, Y. I. Park, and J. H. Kim, “Properties of hydrogenated amorphous silicon thin film transistors fabricated at 150°C,” J. Non-Cryst. Solids, 266-269, pp. 1315-1319, 2000.
[15] T.-K. Kim, T.-H. Ihn, B.-I. Lee, and S.-K. Joo “High-performance low- temperature poly-silicon thin film transistors fabricated by new metal-induced lateral crystallization process,” Jpn. J. Appl. Phys., 37, pp. 4244-4247, 1998.
[16] M. Kimura, I. Yudasaka, S. Kanbe, H. Kobayashi, H. Kiguchi, S.-I. Seki, S. Miyashita, T. Shimoda, T. Ozawa, K. Kitawada, T. Nakazawa, W. Miyazawa, and H. Ohshima, “Low-temperature polysilicon thin-film transistor driving with integrated driver for high-resolution light emitting polymer display,” IEEE Trans. Electron Devices, 46, 12, pp. 2282-2288, 1999.
[17] D. H. Levy, D. Freeman, S. F. Nelson, P. J. Cowdery-Corvan, and L. M. Irving , “Stable ZnO thin film transistors by fast open air atomic layer deposition,” Appl. Phys. Lett., 92, p. 192101, 2008.
[18] D. H. Redinger, “Lifetime Modeling of ZnO Thin-Film Transistors,” IEEE Trans. Electron Devices, 57, 12, pp. 3460-3465, 2010.
[19] W.-S. Cheong, M.-K. Ryu, J.-H Shin, S.-H. K. Park, and C.-S. Hwang , “Transparent thin-film transistors with zinc oxide semiconductor fabricated by reactive sputtering using metallic zinc target,” Thin Solid Films, 516, pp. 8159-8164, 2008
[20] A. Suresh, P. Wellenius, A. Dhawan, and J. Muth, “Room temperature pulsed laser deposited indium gallium zinc oxide channel based transparent thin film transistors,” Appl. Phys. Lett., 90, 12, p. 123512, 2007.
[21] D. Stryakhilev, J.-S. Park, J. Lee, T. W. Kim, Y. S. Pyo, D. B. Lee, E. H. Kim, D. U. Jin, and Y.-G. Mo , “Electrical instability of a-In–Ga–Zn–O TFTs biased below accumulation threshold” Electrochem. Solid-State Lett., 12, 11, pp. J101-J104, 2009.
[22] L.-Y. Su, H. Y. Lin, S.-L. Wang, Y.-H. Yeh, C.-C. Cheng, L. H. Peng, and J.-J. Huang, “Effects of gate-bias stress on ZnO thin-film transistors,” J. Soc. Inf. Disp., 18, 10, pp. 802-806, 2010.
[23] J. K. Jeong, H. W. Yang, J. H. Jeong, Y.-G. Mo, and H. D. Kim, “Origin of threshold voltage instability in indium-gallium-zinc oxide thin film transistors,” Appl. Phys. Lett., 93, 12, p. 123508, 2008.
[24] T. Kamiya, K. Nomura, and H. Hosono, “Present status of amorphous In–Ga–Zn–O thin-film transistors,” Sci. Technol. Adv. Mater., vol. 11, no. 4, p. 044305, 2010.
[25] M.-W. Ma, C.-Y. Chen, W.-C. Wu, C.-J. Su, K.-H. Kao, T.-S. Chao, and T.-F. Lei, “Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: PBTI, NBTI, and hot-carrier stress,” IEEE Trans. Electron Devices, 55, 5, pp. 1153-1160, 2008.
[26] L. Zhang, J. Li, X. W. Zhang, X. Y. Jiang, and Z. L. Zhang, “High performance ZnO-thin-film transistor with Ta2O5 dielectrics fabricated at room temperature,” Appl. Phys. Lett., 95, 7, p. 072112, 2009.
[27] S.-H. K. Park, C.-S. Hwang, H. Y. Jeong, H. Y. Chu, and K. I. Cho, “Transparent ZnO-TFT arrays fabricated by atomic layer deposition,” Electrochem. Solid-State Lett., 11, 1, pp. H10-H14, 2008.
[28] J.-H. Ahn, H.-S. Kim, K. J. Lee, Z. Zhu, E. Menard, R. G. Nuzzo, and J. A. Rogers, “High-speed mechanically flexible single-crystal silicon thin-film transistors on plastic substrates,” IEEE Electron Device Lett., 27, 6, pp. 460-462 2006.
[29] C.-S. Yang, L. L. Smith, C. B. Arthur, and G. N. Parsons, “Stability of low-temperature amorphous silicon thin film transistors formed on glass and transparent plastic substrates,” J. Vac. Sci. Technol. B, 18, 2, pp. 683-689, 2000.
[30] R. Navamathavan, E.-J. Yang, J.-H. Lim, D.-K. Hwang, J.-Y. Oh, J.-H. Yang, J.-H. Jang, and S.-J. Parka, “Effects of electrical bias stress on the performance of ZnO-based TFTs fabricated by rf magnetron sputtering,” J. Electrochem. Soc., 153, 5, pp. G385-G388, 2006.
[31] S. K. Kim, K. S. Lee, and J. Jang, “Creation of interface states between SiO, and a-Si:H in a-Si:H thin film transistors by bias-stress,” J. Non-Cryst. Solids, 198-200, pp. 428-431, 1996.
[32] M. Kimura, T. Nakanishi, K. Nomura, T. Kamiya, and H. Hosono, “Trap densities in amorphous-InGaZnO 4 thin-film transistors,” Appl. Phys. Lett., 92, 3, p. 133512, 2008.
[33] G. H. Kim, W. H. Jeong, B. D. Ahn, H. S. Shin, H. J. Kim, H. J. Kim, M. K. Ryu, K. B. Park, J. B. Seon, and S. Y. Lee, “Investigation of the effects of Mg incorporation into InZnO for high-performance and high-stability solution-processed thin film transistors,” Appl. Phys. Lett., 96, 16, p. 163506 2010.
[34] C.-J. Ku, Z. D., P. I. Reyes, Y. Lu, Y. Xu, C.-L. Hsueh, and E. Garfunkel, “Effects of Mg on the electrical characteristics and thermal stability of MgxZn1-xO thin film transistors,” Appl. Phys. Lett., 98, 12, p. 123511, 2011.
[35] Y. Kwon, Y. Li, Y. W. Heo, M. Jones, P. H. Holloway, D. P. Norton, Z. V. Park , and S. Li, “Enhancement-mode thin-film field-effect transistor using phosphorus-doped (Zn,Mg)O channel,” Appl. Phys. Lett., 84, 15, pp. 2685-2687, 2004.
[36] A. Ohtomo, M. Kawasaki, T. Koida, K. Masubuchi, H. Koinuma, Y. Sakurai, Y. Yoshida, T. Yasuda, and Y. Segawa, “MgxZn1–xO as a II–VI widegap semiconductor alloy,” Appl. Phys. Lett., 72, 19, pp. 2466-2468, 1998.
第二章參考文獻:
[1] M. J. Powell, “The physics of amorphous-silicon thin-film transistors,” IEEE Trans. Electron Devices, 36, 12, pp. 2753-2763, 1989.
[2] D. Hong, G. Yerubandi, H. Q. Chiang, M. C. Spiegelberg, and J. F. Wager, “Electrical modeling of thin-film transistors,” Critical Reviews in Solid State and Materials Sciences, 33, 2, pp. 101-132, 2008.
[3] A. J. Snell, K. D. Mackenzie, W. E. Spear, and P. G. LeComber, “Application of amorphous silicon field effect transistors in addressable liquid crystal display panels,” Appl. Phys. A, 24, 4, pp. 357-362, 1981.
[4] C. R. Kagan, P. Andry, Thin-Film Transistors, Marcel Dekker, Inc., pp. 37-39, 2003.
[5] M. J. Powell, C. van Berkel, I. D. French, and D. H. Nicholls, “Bias dependence of instability mechanisms in amorphous silicon thin-film transistors,” Appl. Phys. Lett., 51, 16, pp. 1242-1244, 1987.
[6] W. B. Jackson, and M. D. Moyer, “Creation of near-interface defects in hydrogenated amorphous silicon-silicon nitride heterojunctions: the role of hydrogen,” Phys. Rev. B, 36, 6217, pp. 6217-6220, 1987.
[7] C. R. Kagan, P. Andry, Thin-Film Transistors, Marcel Dekker, Inc., pp. 86-87, 2003.
[8] J. S. Jung, K. S. Son, K.-H. Lee, J. S. Park, T. S. Kim, J.-Y. Kwon, K.-B. Chung, J.-S. Park, B. Koo, and S. Lee, “The impact of SiNx gate insulators on amorphous indium-gallium-zinc oxide thin film transistors under bias-temperature- illumination stress,” Appl. Phys. Lett., 96, 19, p. 193506, 2010.
[9] J. K. Jeong, H. W. Yang, J. H. Jeong, Y.-G. Mo, and H. D. Kim, “Origin of threshold voltage instability in indium-gallium-zinc oxide thin filmtransistors,” Appl. Phys. Lett., 93, 12, p. 123508, 2008.
[10] A.V. Gelatos and J. Kanicki, “Bias stress‐induced instabilities in amorphous silicon nitride/hydrogenated amorphous silicon structures : Is the “carrier‐induced defect creation” model correct?,” Appl. Phys. Lett., 57, 12, pp. 1197-1199, 1990.
[11] F. R. Libsch and J. Kanicki, “Bias-stress-induced stretched-exponential time dependence of charge injection and trapping in amorphous thin-film transistors,” Appl. Phys. Lett., 62, 11, pp. 1286-1288, 1993.
[12] K.-I Choi, D.-H. Nam, J.-G. Park, S.-S. Park, W.-H. Choi, I.-S. Han, J.-K. Jeong, H.-D. Lee, and G.-W. Lee, “Instability dependent upon bias and temperature stress in amorphous-indium gallium zinc oxide (a-IGZO) thin-film transistors,” J. Soc. Inf. Disp., 18, 1, pp. 108-112, 2010.
[13] Y.-K. Moon, S. Lee, D.-H. Kim, D.-H. Lee, C.-O. Jeong, and J.-W. Park, “Application of DC magnetron sputtering to deposition of InGaZnO films for thin film transistor devices,” Jpn. J. Appl. Phys., 48, p. 031301, 2009.
[14] A. Suresh and J. F. Muth, “Bias stress stability of indium gallium zinc oxide channel based transparent thin film transistors,” Appl. Phys. Lett., 92, 3, p. 033502, 2008.
[15] J.-M. Lee, I.-T. Cho, J.-H. Lee, and H.-I. Kwon, “Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors,” Appl. Phys. Lett., 93, 9, p. 093504, 2008.
[16] S.-Y. Sung, J. H. Choi, U. B. Han, K. C. Lee, and J.-H. Lee, “Effects of ambient atmosphere on the transfer characteristics and gate-bias stress stability of amorphous indium-gallium-zinc oxide thin-film transistors,” Appl. Phys. Lett., 96, 10, p. 102107, 2010.
[17] J.-J. Kim, W. Lim, S. J. Pearton, D. P. Norton, and Y.-W. Heo, “Electrical instability of a-In–Ga–Zn–O TFTs biased below accumulation threshold,” Electrochem. Solid-State Lett., 12, 11, pp. J101-J104, 2009.
[18] J.-W. Tsai, C.-Y. Huang, Y.-H. Tai, F.-C. Su, F.-C. Luo, H.-C. Tuan, and H.-C. , “Reducing threshold voltage shifts in amorphous silicon thin film transistors by hydrogenating the gate nitride prior to amorphous silicon deposition,” Appl. Phys. Lett., 71, 9, pp. 1237-1239, 1997.
[19] S.-C. Kao, H.-W. Zan, J.-J. Huang, and B.-C. Kung, “Self-heating effect on bias-stressed reliability for low-temperature a-Si:H TFT on flexible substrate,” IEEE Trans. Electron Devices, 57, 3, pp. 588-593, 2010.
[20] J. B. Choi, D. C. Yun, Y. I. Park, and J. H. Kim, “Properties of hydrogenated amorphous silicon thin film transistors fabricated at 150°C,” J. Non-Cryst. Solids, 266-269, pp. 1315-1319, 2000.
[21] H. Kavak, C. Gruber, H. Shanks, A. Landin, A. Constant, and S. Burns, “Thin film transistors on polyimide substrates,” J. Non-Cryst. Solids, 266-269, pp. 1325-1328, 2000.
[22] R. Shringarpure, S. Venugopal, L. T. Clark, D. R. Allee, and E. Bawolek, “Localization of gate bias induced threshold voltage degradation in a-Si:H TFTs,” IEEE Electron Device Lett., 29, 1, pp. 93-95, 2008.
[23] J. H. Choi, U. B. Han, K. C. Lee, J.-H. Lee, and J.-J. Kim, “Transfer characteristics and bias-stress stability of amorphous indium zinc oxide thin-film transistors,” J. Vac. Sci. Technol. B, 27, 2, pp. 622-625, 2009.
[24] D. H. Levy, D. Freeman, S. F. Nelson, P. J. Cowdery-Corvan, and L. M. Irving, “Stable ZnO thin film transistors by fast open air atomic layer deposition,” Appl. Phys. Lett., 92, 19, p. 192101, 2008.
[25] R. B. M. Cross and M. M. De Souza, “Investigating the stability of zinc oxide thin film transistors,” Appl. Phys. Lett., 89, 26, p. 263513, 2006.
[26] L.-Y. Su, H.-Y. Lin, S.-L. Wang, Y.-H. Yeh, C.-C. Cheng, L. H. Peng, and J.-J. Huang, “Effects of gate-bias stress on ZnO thin-film transistors,” J. Soc. Inf. Disp., 18, 10, pp. 802-806, 2010.
[27] L. Zhang, J. Li, X. W. Zhang, D. B. Yu, H. P. Lin, Khizar-ul-Haq, X. Y. Jiang, and Z. L. Zhang, “The influence of the SiO2 deposition condition on the ZnO thin-film transistor performance,” Superlatt. Microstruct., 48, 2, pp. 198-205, 2010.
[28] D. H. Redinger, “Lifetime modeling of ZnO thin-film transistors,” IEEE Trans. Electron Devices, 57, 12, pp. 3460-3465, 2010.
[29] S. J. Lim, J.-M. Kim, D. Kim, S. Kwon, J.-S. Park, and H. Kim, “Atomic layer deposition ZnO:N thin film transistor: The effects of N concentration on the device properties,” J. Electrochem. Soc., 157, 2, pp. H214-H218, 2010.
[30] E. M. C. Fortunato, P. M. C. Barquinha, A. C. M. B. G. Pimentel, A. M. F. Gonçalves, A. J. S. Marques, L. M. N. Pereira, and R. F. P. Martins, “Fully transparent ZnO thin-film transistor produced at room temperature,” Adv. Mater., 17, 5, pp. 590-594, 2005.
[31] M. Kimura, T. Nakanishi, K. Nomura, T. Kamiya, and H. Hosono, “Trap densities in amorphous-InGaZnO4 thin-film transistors,” Appl. Phys. Lett., 92, 13, p. 133512, 2008.
[32] W.-S. Kim, Y.-K. Moon, S. Lee, B.-W. Kang, K.-T. Kim, J.-H. Lee, J.-H. Kim, B.-D. Ahn, and J.-W. Park, “Amorphous indium gallium zinc oxide semiconductor thin film transistors using O2 plasma treatment on the SiNx gate insulator,” Jpn. J. Appl. Phys., 49, p. 08JF02, 2010.
[33] H.-W. Zan, W.-T. Chen, C.-W. Chou, C.-C. Tsai, C.-N. Huang, and H.-W. Hsueh, “Low Temperature Annealing with Solid-State Laser or UV lamp irradiation on amorphous IGZO thin-film transistors,” Electrochem. Solid-State Lett., 13, 5, pp. H144-H146, 2010.
[34] B. D. Ahn, W. H. Jeong, H. S. Shin, D. L. Kim, H. J. Kim, J. K. Jeong, S.-H. Choi, and M.-K. Han, “Effect of excimer laser annealing on the performance of amorphous indium gallium zinc oxide thin-film transistors,” Electrochem. Solid-State Lett., 12, 12, pp. H430-H432, 2009.
[35] C. Chen, K. Abe, H. Kumomi, and J. Kanicki, “Density of states of a-InGaZnO from temperature-dependent field-effect studies,” IEEE Trans. Electron Devices, 56, 6, pp. 1177-1183, 2009.
[36] C.-J. Ku, Z. D., P. I. Reyes, Y. Lu, Y. Xu, C.-L. Hsueh, and E. Garfunkel, “Effects of Mg on the electrical characteristics and thermal stability of MgxZn1-xO thin film transistors,” Appl. Phys. Lett., 98, 12, p. 123511, 2011.
第三章參考文獻:
[1] http://mysite.du.edu/~jcalvert/phys/dischg.htm
[2] 賴耿陽,“IC 製程之濺射技術”,復漢出版社,1997
[3] http://www.umms.sav.sk/index.php?ID=415
[4] http://eshare.stut.edu.tw/EshareFile/2009_11/2009_11_13e6f13f.pdf
[5] http://www.memsnet.org/mems/processes/deposition.html
[6] http://hyperphysics.phy-astr.gsu.edu/hbase/quantum/bragg.html
[7] http://www.me.tnu.edu.tw/~me010/Precision_Equipment_Lab/SEM_web/TNIT_lab_SEMintroduction_down.htm
第四章參考文獻:
[1] J.-H. Boo, S.-B. Lee, K.-S. Yu, W. Koh, and Y. Kim,”Growth of magnesium oxide thin films using single molecular precursors by metal organic chemical vapor deposition,” Thin Solid Film, 341, 1-2, pp. 63-67, 1999.
[2] A. Ohtomo, S. Takagi, K. Tamura, T. Makino, Y. Segawa, H. Koinuma, and M. Kawasaki, “Photo-irresponsive thin-film transistor with MgxZn1-xO channel,” Jpn. J. Appl. Phys., 45 , 27, pp. L694-L696, 2006.
[3] R. B. M. Cross, M. M. D. Souza, S. C. Deane, and N. D. Young, “A comparison of the performance and stability of ZnO-TFTs with silicon dioxide and nitride as gate insulators,” IEEE Trans. Electron Devices, vol. 55, no. 5, pp. 1109-1115, 2008.
[4] L.-Y. Su, H.-Y. Lin, S.-L. Wang, Y.-H. Yeh, C.-C. Cheng, L. H. Peng, and J.-J. Huang, “Effects of gate-bias stress on ZnO thin-film transistors,” J. Soc. Inf. Displ., 18, 10, pp. 802-806, 2010.
[5] C.-J. Ku, Z. Duan, P. I. Reyes, Y. Lu, Y. Xu, C.-L. Hsueh, and E. Garfunkel, “Effects of Mg on the electrical characteristics and thermal stability of MgxZn1-xO thin film transistors,” Appl. Phys. Lett., 98, 12, p. 123511, 2011.
[6] J.-M. Lee, I.-T. Cho, J.-H. Lee, and H.-I. Kwon, “Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors,” Appl. Phys. Lett., 93 , 9, p. 093504, 2008.
[7] T.-C. Fung, K. Abe, H. Kumomi, and J. Kanicki, “Electrical instability of rf sputter amorphous In-Ga-Zn-O thin-film transistors,” J. Disp. Technol., 5, 12, pp. 452-461, 2009.
[8] S.-Y. Huang, T.-C. Chang, M.-C. Chen, S.-C. Chen, C.-T. Tsai, M.-C. Hung, C.-H. Tu, C.-H. Chen, J.-J. Chang, and W.-L. Liauc, “Effects of ambient atmosphere on electrical characteristics of Al2O3 passivated InGaZnO thin film transistors during positive-bias-temperature-stress operation,” Electrochem. Solid-State Lett., 14, 4, pp. H177-H179, 2011.
[9] Y. Kamada, S. Fujita, M. Kimura, T. Hiramatsu, T. Matsuda, M. Furuta, and T. Hirao, “Effects of chemical stoichiometry of channel region on bias instability in ZnO thin-film transistors,” Appl. Phys. Lett., 98 , 10, p. 103512, 2011.
[10] M.-W. Ma, C.-Y. Chen, W.-C. Wu, C.-J. Su, K.-H. Kao, T.-S. Chao, and T.-F. Lei, “Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: PBTI, NBTI, and hot-carrier stress,” IEEE Trans. Electron Devices, 55, 5, pp. 1153-1160, 2008.
[11] C.-T. Tsai, T.-C. Chang, S.-C. Chen, I. Lo, S.-W. Tsao, M.-C. Hung, J.-J. Chang, C.-Y. Wu, and C.-Y. Huang, “Influence of positive bias stress on N2O plasma improved InGaZnO thin film transistor” Appl. Phys. Lett., 96 , 24, p. 242105, 2010.
[12] J. K. Jeong, H. W. Yang, J. H. Jeong, Y.-G. Mo, and H. D. Kim, “Origin of threshold voltage instability in indium-gallium-zinc oxide thin film transistors,” Appl. Phys. Lett., 93, 12, p.123508, 2008.
[13] D. N. Kouvatsos and D. Davazoglou, “Gate/drain bias-induced degradation effects in TFTs fabricated in unhydrogenated SPC polycrystalline silicon films,” Thin Solid Films, 426, 1-2, pp. 250-257, 2003.
[14] H.-S. Jung, S.-H. Rha, H. K. Kim, J. H. Kim, S.-J. Won, J. Lee, S. Y. Lee, C. S. Hwang, J.-M. Park, W.-H. Kim, M.-W. Song, and N.-I. Lee, “Turn-around effect of Vth shift during the positive bias temperature instability of the n-type transistor with HfOxNy gate dielectrics,” IEEE Electron Device Lett., 31, 12, pp. 1479-1481, 2010.
[15] I.-T. Cho, J.-M. Lee, J.-H. Lee, and H.-I. Kwon, “Charge trapping and detrapping characteristics in amorphous InGaZnO TFTs under static and dynamic stresses,” Semicond. Sci. Technol., 24, 1, pp. 015013, 2009.
[16] H.-C. Cheng, C.-Y. Huang, J.-W. Lin, and Jerry J.-H. Kung, “The reliability of amorphous silicon thin film transistors for LCD under DC and AC stresses,” Solid-State and Integrated Circuit Technology, 1998 5th International Conference.
[17] C.-Y. Huang, T.-H. Teng, J.-W. Tsai, and H.-C. Cheng, “The instability mechanisms of hydrogenated amorphous silicon thin film transistors under AC bias stress,” Jpn. J. Appl. Phys., 39, 7, pp. 3867-3871, 2000.
[18] D. Zhou, M. Wang, H. Li, and J. Zhou, “Stability of a-Si thin film transistors under negative gate bias stress,” Physical and Failure Analysis of Integrated Circuits (IPFA), 2010 17th IEEE International Symposium.
[19] J. C. Liao, Y. K. Fang, C. H. Kao, and C. Y. Cheng, “Dynamic Negative Bias Temperature Instability (NBTI) of Low-Temperature Polycrystalline Silicon (LTPS) Thin-Film Transistors,” IEEE Electron Device Lett., 29, 5, pp. 477-479, 2008.
[20] C. Shen, H. Y. Yu, X. P. Wang, M.-F. Li, Y.-C. Yeo, Daniel S. H. Chan, K. L. Bera, and D.L. Kwong, “Frequency dependent dynamic charge trapping in HfO2 and threshold voltage instability in MOSFETs,” IEEE International Reliability Physics Symposium Proceedings, pp. 601-602, 2004
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8991-
dc.description.abstract本論文主要探討兩種退火條件下氧化鋅鎂下閘極薄膜電晶體(thin-film transistor)在不同溫度下之閘極偏壓穩定性。由文獻中得知,在氧化鋅中添加鎂可以減少氧空缺的產生,進而增加材料的電穩定性。另一方面,銦在地球的存量相對稀少,因此本論文針對無銦的氧化鋅鎂薄膜電晶體進行研究。
X光繞射(XRD)分析氧化鋅鎂的單層膜發現200°C退火的薄膜只有些許的峰值偏移,而350°C退火的薄膜有較大的峰值偏移,並且也有較小的半高全寬(full width at half-maximum),表示在350°C的退火條件下有較多鎂取代鋅與較佳的結晶性。
接著於變溫量測中,200°C退火的電晶體隨溫度升高有比較不一致的電性變化,而350°C退火的電晶體則相當一致。在常溫正偏壓穩定性測試中,兩者皆沒有明顯的次臨界擺幅(subthreshold swing)變化,顯示臨界電壓(threshold voltage)的偏移機制為電荷捕陷(charge trapping),而350°C退火的電晶體有比較少的臨界電壓偏移,顯示350°C退火的電晶體穩定性較佳。於變溫的正偏壓測試中,隨著環境溫度升高以及偏壓時間增加,200°C退火的電晶體轉換特性曲線(transfer characteristic curve)出現駝峰(hump)現象,此一現象在較高溫的350°C退火的薄膜電晶體則沒有發現。而此一駝峰現象在外加閘極偏壓移徐後,會完全回復。因此被認為是由閘極偏壓所造成之介穩態現象。這一個電晶體轉換特性曲線次臨界區域的駝峰現象,機制尚不完全明朗。一般認為和閘極偏壓導致的介穩態(meta-stable)缺陷有關。在較高溫進行閘極偏壓測試時,所造成的介穩態中性氧空缺可能激發成正一價或正二價的氧空缺,所釋放的電子在通道層形成漏電通道(leakage path),而造成電晶體的早期導通狀態,因此在電晶體轉換特性曲線之次臨界區域造成駝峰現象。
在負偏壓下並沒有駝峰的現象出現,然而,於高溫負偏壓測試時,200°C退火的臨界電壓變化有折返(turn-around)現象,主要由缺陷產生(defect creation)機制與電荷捕陷互相競爭造成。相較上述的直流偏壓,交流偏壓測試有較小的臨界電壓偏移,但是隨著偏壓訊號的頻率增加,臨界電壓偏移量也隨著增加,此一現象可能是由於被捕陷的載子回復較慢導致。
總體而言,350°C退火的氧化鋅鎂薄膜電晶體在各方面的穩定性測試中,皆相較於200°C退火的電晶體來的穩定,這可能是由於較高溫退火電晶體的通道層結晶中有較多鎂的取代鋅以及較好的氧化鋅鎂結晶品質所導致。
zh_TW
dc.description.abstractThis thesis reports the experimental studies on the gate-bias temperature stability of inverted staggered bottom-gate Mg0.05Zn0.95O thin-film transistors (TFT). According to literatures, the addition of Mg into ZnO related materials can reduce the oxygen vacancies due to higher ionic character of Mg-O than Zn-O bonds. In addition, indium is rare in earth. Therefore, we chose indium free MgZnO TFTs as our research target.
ZnO films crystallize easily, even when grown at room temperature. With the application of post-deposition annealing at 200°C, the (002) peak increased slightly, indicating the substitution of a small portion of Mg for Zn in the ZnO crystals. This substitution reduced the lattice constant of wurtzite ZnO, caused by the slightly smaller ionic radius of Mg2+ than that of Zn2+. Moreover, as the annealing temperature increased to 350°C, grains grew and the crystallinity of Mg0.05Zn0.95O improved, as denoted by a decrease of full width at half maximum (FWHM) of (002) peak. Furthermore, (002) the peak shifted even higher, indicating the substitution of more Zn by Mg in the ZnO crystals.
In the positive gate-bias stability test at room temperature, the subthreshold swing was nearly unchanged for the devices annealed at two different annealing conditions, revealing that the main mechanism for the threshold voltage (Vth) shift was charge trapping. The 350°C-annealed TFT showed less Vth shift, indicating better device stability. As the positive gate-bias stress applied to TFTs at elevated temperatures, humps occurred in the subthreshold region of the transfer curves in the 200°C-annealed TFT, and became severe as temperature and stressing time increases. The hump phenomenon was much less significant in 350°C annealed TFTs; merely a degradation of SS was observed at 80°C, the highest testing temperature in this study. The hump disappeared shortly after removing the positive gate-bias, suggesting that this phenomenon was meta-stable and was resulted from gate-bias induced electric field. This hump phenomenon might have been due to the creation of meta-stable oxygen vacancies in which the neutral vacancies were thermally excited into ionized states and released electrons into the active layer to form a leakage path, when TFTs were subjected to gate-bias stressing at elevated temperatures.
The humps were not identified in the transfer curves when TFTs were subjected to negative bias stress. Instead, a turn-around of Vth shift occurred in the 200°C-annealed TFT. It was attributed to the competing mechanisms of the defect creation and the charge trapping. In the AC bias stress, Vth shift was less severe to the DC bias stress. Nevertheless, the Vth shift increased with the increasing frequency of AC bias stress. It may come from the slow recovery of trapped charges.
In conclusion, the 350°C-annealed TFT showed a better bias temperature stability. The more substitution of Zn by Mg and better crystallinity help improve the stability of MgZnO TFTs.
en
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Previous issue date: 2011
en
dc.description.tableofcontents誌謝........................................................................i
中文摘要....................................................................ii
英文摘要................................................................... iii
目錄........................................................................v
圖目錄......................................................................vii
表目錄......................................................................xi
第一章 簡介.................................................................1
1.1薄膜電晶體發展背景.......................................................1
1.2研究動機.................................................................2
1.3論文架構.................................................................3
1.4第一章參考文獻...........................................................4
第二章 理論及文獻回顧.......................................................8
2.1薄膜電晶體簡介...........................................................8
2.2薄膜電晶體工作原理.......................................................9
2.3薄膜電晶體之特徵參數....................................................10
2.4不同通道層之薄膜電晶體穩定性比較........................................12
2.5低溫製程之薄膜電晶體....................................................15
2.6汲極電流之活化能........................................................15
2.7第二章參考文獻..........................................................17
第三章 實驗步驟及方法......................................................21
3.1薄膜成長儀器及原理......................................................21
3.1.1電漿原理..............................................................21
3.1.2濺鍍系統..............................................................22
3.1.3磁控濺鍍..............................................................23
3.1.4電子束蒸鍍(electric beam evaporation).................................24
3.2微影製程................................................................24
3.3薄膜電晶體 製作流程.....................................................26
3.4分析及量測儀器..........................................................28
3.4.1 X光繞射儀(X-ray diffraction).........................................28
3.4.2表面輪廓儀............................................................29
3.4.3掃描式電子顯微鏡......................................................29
3.4.4電性量測架構..........................................................31
3.5第三章參考文獻..........................................................32
第四章 實驗結果與討論......................................................33
4.1薄膜性質分析............................................................33
4.1.1氧化鎂薄膜(介電層)性質分析..........................................33
4.1.2氧化鋅鎂薄膜(通道層)性質分析........................................35
4.2不同退火後處理之電性....................................................38
4.3不同退火後處理熱穩定性..................................................43
4.4不同退火後處理電穩定性..................................................46
4.4.1電穩定性與電熱穩定性比較..............................................46
4.4.2不同閘極偏壓極性之穩定性..............................................56
4.4.3不同閘極偏壓頻率之電穩定性 (AC測試)...................................65
4.5第四章參考文獻..........................................................71
第五章 結論與未來展望......................................................74
5.1結論....................................................................74
5.2未來展望................................................................75
dc.language.isozh-TW
dc.title下閘極氧化鋅鎂薄膜電晶體之電穩定性研究zh_TW
dc.titleThe Study on the Electrical Stability of Bottom-Gate MgZnO Thin-Film Transistorsen
dc.typeThesis
dc.date.schoolyear99-2
dc.description.degree碩士
dc.contributor.oralexamcommittee陳敏璋,陳奕君,林致廷
dc.subject.keyword氧化物薄膜電晶體,氧化鋅鎂,氧化鎂,偏壓穩定性,熱穩定性,zh_TW
dc.subject.keywordoxide TFTs,MgZnO,MgO,gate-bias stability,thermal stability,en
dc.relation.page75
dc.rights.note同意授權(全球公開)
dc.date.accepted2011-08-16
dc.contributor.author-college工學院zh_TW
dc.contributor.author-dept應用力學研究所zh_TW
顯示於系所單位:應用力學研究所

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