MOS 電流模式邏輯應用於數位電路之設計

Abstract

本文提出了一種用於實現Current Mode Logic (CML)電路的數位設計流程。CML電路是全差動電路，不能以目前商用Computer-Aided Design (CAD)工具直接進行設計，必須開發一種有別以往的設計方法，以便使用標準CAD工具自動化設計CML電路。首先設計CML標準元件，並生成商業CAD工具所需的元件庫，在單端流程進行合成、佈局及繞線，讓商業CAD工具將CML電路視為標準的CMOS邏輯電路，同時開發了一種自動將單端電路轉換為全差動CML電路的演算法。在驗證完設計流程後，使用UMC的0.18微米製程設計了一個100MHz的sigma-delta modulation digital-to-analog converter (DAC)。本研究相較於以前的CML設計自動化流程不同，本研究成功的解決晶片內金屬層密度和大規模Design Rule Check (DRC)問題，並以此設計流程下線了一個實體晶片。

In this paper a digital design flow for implementing Current Mode Logic (CML) circuits is presented. CML circuits are fully differential and are not directly supported by commercial Computer-Aided Design (CAD) tools. A special design methodology must be developed such that design of CML circuits can be automated using standard CAD tools. CML standard cells are first designed and the required libraries required for commercial CAD tools are then generated. Synthesis and place & route (P&R) in a single-ended domain that tricks commercial CAD tools as treating CML circuits as standard CMOS logic circuits. An algorithm that automatically converts single-ended circuits into fully differential CML circuits is developed. After validation of the design flow, a 100-MHz sigma-delta modulation Digital-to-analog Converter (DAC) was taped out using UMC's 0.18um process. Unlike previous works on CML design automation, this work ended with a real fabricated chip, where lots of effort were put in to resolve density and large scale Design Rule Check (DRC) problems.