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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳昭宏 | zh_TW |
| dc.contributor.advisor | Jau-Horng Chen | en |
| dc.contributor.author | 李允中 | zh_TW |
| dc.contributor.author | Yun-Chung Lee | en |
| dc.date.accessioned | 2023-08-16T17:12:43Z | - |
| dc.date.available | 2023-11-09 | - |
| dc.date.copyright | 2023-08-16 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-08-09 | - |
| dc.identifier.citation | [1]M. Yamashina, H. Yamada, “An MOS current mode logic (MCML) circuit for low-power subGHz processors,” in IEICE Transactions, E75-C, October 1992.
[2]S. Badel, C. Baltaci, A. Cevrero and Y. Leblebici, “Design automation for differential MOS current-mode logic circuits,” Springer International Publishing, 2019. [3]H. Reyserhove and W. Dehaene, “Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors,” Springer, 2019. [4]Z-V Chia, S¬-Y-S Ng and M. Je, “Current mode logic circuits for 10-bit 5 GHz high speed digital to analog converter,” International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering 7, no. 9, 2013. [5]Y. Ling, W. Ni, Y. Shi and F. F. Dai, “A 10-bit 2GHz current-steering CMOS D/A converter,” in 2007 IEEE International Symposium on Circuits and Systems, pp. 737-740, 2007. [6]F. Cannillo, C. Toumazou, and T. S. Lande, “Bulk-drain connected load for subthreshold MOS current-mode logic,” Electronics Letters 43, no. 12, 2007. [7]J. Musicer and J. Rabaey, “MOS Current Mode Logic for Low Power, Low Noise CORDIC Computation in Mixed-Signal Environments,” in Proc. International Symposium on Low Power Electronics and Design (ISLPED), pp. 102 - 107, 2000. [8]M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, and H. Yamada, "A GHz MOS Adaptive Pipeline Technique Using MOS Current-Mode Logic, " IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 784 - 791, 1996. [9]S. Badel, I. Hatirnaz and Y. Leblebici, “A semi-automated design of a MOS current-mode logic standard cell library from generic components,” in IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) , 2005. [10]S. Badel, I. Hatirnaz and Y. Leblebici and E. J. Brauer, “Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells,” in 2006 IFIP International Conference on Very Large Scale Integration, pp. 234-238, 2006. [11]I. Hatirnaz, S. Badel and Y. Leblebici, “Towards a unified top-down design flow for fully differential logic blocks with improved speed and noise immunity,” Research in Microelectronics and Electronics, 2005 PhD, vol. 1, pp. 89-92, 2005. [12]S. Badel, E. Güleyüpoǧlu, Ö. Inaç, A.P. Martinez, P. Vietti, F. K. Gürkaynak, and Y. Leblebici, “A generic standard cell design methodology for differential circuit styles,” in Proceedings of the conference on Design, automation and test in Europe, pp. 843-848, 2008. [13]S.R.P. Sinha and N. Tiwari, “Design and Analysis of Dynamic Current Mode Full Adder with reduced Power and Delay,” International Journal of Science and Research (IJSR), 2015. [14]M. Fouad, H.H. Amer, A.H. Madian and M.B. Abdelhalim, “Current mode logic testing of XOR/XNOR circuit： a case study,” Circuits and Systems, Scientific Research Publishing, vol.4, pp. 364-368, August 2013. [15]H. Chen, G. Guo, Q. Lai, Y. Zhang, J. Han and Y. Yan, “0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate,” IEICE Electronics Express 14, no. 12, 2017. [16]Z. Toprak and Y. Leblebici, “Low-power current mode logic for improved DPA-resistance in embedded systems,” in 2005 IEEE International Symposium on Circuits and Systems, pp. 1059-1062, 2005. [17]R.R. Gujjula, C. Perumal, P. Kodali and V.R. Bodapati, “Design and analysis of dual-mode numerically controlled oscillators based controlled oscillator frequency modulation,” International Journal of Electrical and Computer Engineering 12, no. 5, 2022. [18]P. Ju, K. Suyama, P.F. Ferguson and W. Lee, “A 22-kHz multibit switched-capacitor sigma-delta D/A converter with 92 dB dynamic range,” in IEEE Journal of Solid-State Circuits, vol. 30, no. 12, pp. 1316-1325, Dec. 1995. [19]Cadence, SKILL Language User Guide (v06.70), January 2007 | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/89119 | - |
| dc.description.abstract | 本文提出了一種用於實現Current Mode Logic (CML)電路的數位設計流程。CML電路是全差動電路，不能以目前商用Computer-Aided Design (CAD)工具直接進行設計，必須開發一種有別以往的設計方法，以便使用標準CAD工具自動化設計CML電路。首先設計CML標準元件，並生成商業CAD工具所需的元件庫，在單端流程進行合成、佈局及繞線，讓商業CAD工具將CML電路視為標準的CMOS邏輯電路，同時開發了一種自動將單端電路轉換為全差動CML電路的演算法。在驗證完設計流程後，使用UMC的0.18微米製程設計了一個100MHz的sigma-delta modulation digital-to-analog converter (DAC)。本研究相較於以前的CML設計自動化流程不同，本研究成功的解決晶片內金屬層密度和大規模Design Rule Check (DRC)問題，並以此設計流程下線了一個實體晶片。 | zh_TW |
| dc.description.abstract | In this paper a digital design flow for implementing Current Mode Logic (CML) circuits is presented. CML circuits are fully differential and are not directly supported by commercial Computer-Aided Design (CAD) tools. A special design methodology must be developed such that design of CML circuits can be automated using standard CAD tools. CML standard cells are first designed and the required libraries required for commercial CAD tools are then generated. Synthesis and place & route (P&R) in a single-ended domain that tricks commercial CAD tools as treating CML circuits as standard CMOS logic circuits. An algorithm that automatically converts single-ended circuits into fully differential CML circuits is developed. After validation of the design flow, a 100-MHz sigma-delta modulation Digital-to-analog Converter (DAC) was taped out using UMC's 0.18um process. Unlike previous works on CML design automation, this work ended with a real fabricated chip, where lots of effort were put in to resolve density and large scale Design Rule Check (DRC) problems. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2023-08-16T17:12:43Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2023-08-16T17:12:43Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 ii ABSTRACT iii 目錄 iv 圖目錄 vi 表目錄 viii 第1章 緒論 1 1.1 研究背景與動機 1 1.2 電流模式邏輯(Current Mode Logic, CML) 2 第2章 CML設計方法 4 2.1 高速CML自動化設計方法 4 2.2 低功耗CML自動化設計方法 6 2.3 設計理念 8 第3章 設計流程之改良及實現 9 3.1 元件庫準備 10 3.1.1 標準元件原理圖設計和佈局 10 3.1.2 元件庫生成14 3.2 單端流程 17 3.2.1 合成 18 3.2.2 佈局及繞線 18 3.3 差動流程 22 3.4 驗證模擬 26 第4章 結果與討論 28 4.1 設計流程結果 28 4.2 CML和CMOS電路表現比較 30 4.3 設計流程最佳化 33 4.4 設計流程驗證 40 4.4.1 晶片架構及原理 40 4.4.2 晶片的佈局和實現 44 4.4.3 驗證與模擬 47 第5章 結論與未來展望 49 5.1 結論 49 5.2 未來展望 49 參考文獻 51 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 電流模式邏輯 | zh_TW |
| dc.subject | 數位設計流程 | zh_TW |
| dc.subject | 差動電路 | zh_TW |
| dc.subject | 高速 | zh_TW |
| dc.subject | 電腦輔助設計 | zh_TW |
| dc.subject | differential circuit | en |
| dc.subject | digital design flow | en |
| dc.subject | high-speed | en |
| dc.subject | current mode logic | en |
| dc.subject | computer-aided design | en |
| dc.title | MOS 電流模式邏輯應用於數位電路之設計 | zh_TW |
| dc.title | Mos Current-mode Logic Applied to Digital Design | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 111-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳怡然;張瑞益;陳彥廷 | zh_TW |
| dc.contributor.oralexamcommittee | Yi-Jan Chen;Ray-I Chang;Yan-Ting Chen | en |
| dc.subject.keyword | 電流模式邏輯,差動電路,數位設計流程,高速,電腦輔助設計, | zh_TW |
| dc.subject.keyword | current mode logic,differential circuit,digital design flow,high-speed,computer-aided design, | en |
| dc.relation.page | 53 | - |
| dc.identifier.doi | 10.6342/NTU202303723 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2023-08-11 | - |
| dc.contributor.author-college | 工學院 | - |
| dc.contributor.author-dept | 工程科學及海洋工程學系 | - |
| 顯示於系所單位： | 工程科學及海洋工程學系 | |
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