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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Chin-Yu Lin | en |
| dc.contributor.author | 林晉宇 | zh_TW |
| dc.date.accessioned | 2021-05-20T20:03:33Z | - |
| dc.date.available | 2014-08-20 | |
| dc.date.available | 2021-05-20T20:03:33Z | - |
| dc.date.copyright | 2009-08-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-18 | |
| dc.identifier.citation | [1]Behzad Razavi, Principles of Data Conversion System Design. 1st Ed., Wiley-Interscience, 1995.
[2]B.-G. Lee, B.-M. Min, Gabriele Manganaro, and J. W. Valvano , 'A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC,' IEEE J. of Solid-State Circuits, Vol. 43, pp. 2613-2619, Dec., 2008. [3]Brad Brannon, “Aperture uncertainty and ADC system performance,” AN-501 Application Note, Analog Device. [4] N. D. Dalt, M. Harteneck, C. Sander, and Wiesbauer, “On the jitter requirements of the sampling clock for analog-to-digital converters,” IEEE Trans. Circuits and Syst. I:Fundmental Theory and Applications, vol.49, no.9, pp. 1354-1360, Sep. 2002. [5]M. Shinagawa, Y. Akazawa, and T. Wakimoto, “Jitter analysis of high-speed sampling systems,” IEEE J. Solid-State Circuits, vol. 25, pp. 220-224, Feb. 1990. [6]U. K. Moon, Karti Mayaram, and John T. Stonick, “Spectral analysis of time-domain phase jitter measurements,” IEEE Trans. Circuits and Syst. II, vol.49, no.5, pp. 321-327, May. 2002. [7]F. Herzel and B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” IEEE Trans. Circuits and Syst. II, vol.46, no.31, pp. 56-62, Jan. 1999. [8]Tian Xia and J.-C. Lo, 'Time-to-Voltage Converter for On-Chip Jitter Measurement,' IEEE Trans. Instrumentation and Measurement, vol.52, no.6, pp. 1738-1748, Dec. 2003. [9]E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, 'A High Resolution Time-to-Digital Converters Based on Time-to-Voltage Interpolation,' in Proc. 23rd European Solid-State Circuits Conf. (ESSCIRC),pp. 332-335, 1997. [10]T. E. Rahkonen and J. T. Kostamovaara, 'The Use of Stabilized CMOS Delay Lines for the Digitization of Short Time Intervals,' IEEE J. of Solid-State Circuits, Vol. 28, pp. 887-894, Aug., 1993. [11]V. Ramakrishnan and P. T. Balsara, 'A Wide-Range, High Resolution, Compact, CMOS Time to Digital Converter,' in Proc. 19th Int. Conf. VLSI Design (VLSID’06), Jan., 2006. [12]P. Dudek, S. Szczepanski, and J. Hatfield, 'A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,' IEEE J. of Solid-State Circuits, Vol. 35, pp. 240-247, Feb., 2000. [13]S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, and D. Schmitt-Landsiedel, 'A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion, ' IEEE J. Solid-State Circuits, vol. 43, pp. 1666-1676, July 2008. [14]Poki Chen, S.-I. Liu, and Jingshown Wu, 'A CMOS Pulse-Shrinking Delay Element for Time Interval Measurement,' IEEE Trans. Circuits and Syst. II, vol.47, pp. 954-958, Sep. 2000. [15]J.-P. Jansson, A. Mäntyniemi, and J. Kostamovaara, 'A CMOS Time-to-Digital Converter with Better than 10ps Single-Shot Precision, ' IEEE J. Solid-State Circuits, vol. 41, pp. 1286-1296, June 2006. [16]J. van Valburg and R. J. van de Plassche, 'An 8-b 650-MHz Folding ADC,' IEEE J. Solid-State Circuits, vol. 27, pp. 1662-1666, Dec. 1992. [17]R. Farjad-Rad , W. Dally , H.-T. Ng , R. Senthinathan , M.-J. E. Lee , R. Rathi and J. Poulton, 'A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly Integrated Digital Chips, ' IEEE J. Solid-State Circuits, vol. 37, pp. 1804-1812, Dec. 2002. [18]Keng-Jan Hsiao, 'A DLL-Based Frequency Multiplier for MBOA-UWB System,' Master thesis, National Taiwan University, Taipei, Taiwan, R.O.C., July, 2005. [19]J.-M. Chou, Y.-T. Hsieh, and J.-T. Wu, 'Phase Averaging and Interpolation Using Resistor Strings or Resistor Rings for Multi-Phase Clock Generation,' IEEE Trans. Circuits and Syst. I, vol.53, pp. 984-991, May. 2006. [20]H. Pan and A. A. Abidi 'Spatial Filtering in Flash A/D Converters,' IEEE Trans. Circuits and Syst. II, vol.50, pp. 424-436, Aug. 2003. [21]A. A. Abidi, 'Phase Noise and Jitter in CMOS Ring Oscillators, ' IEEE J. Solid-State Circuits, vol. 41, pp. 1803-1816, Aug. 2006. [22]Behzad Razavi, Design of Analog CMOS Integrated Circuits. 1st Ed., McGraw-Hill, 2001. [23]S. Kim, K. Lee, Y. Moon, D.-K. Jeong, and H. K. Lim, 'A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL, ' IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997. [24]Behzad Razavi, RF Microelectronics, Prentice Hall, 1997. [25]R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, '1.3V 20ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS,' IEEE Trans. Circuits and Syst. II, vol.53, pp. 220-224, Mar. 2006. [26]C.-S. Hwang, Poki Chen, and H.-W. Tsao, 'A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme,' IEEE Trans. Nuclear Science, vol.51, pp. 1349-1352, Aug. 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8894 | - |
| dc.description.abstract | 在現今高速､高精準度的類比數位轉換中，其對取樣時脈抖動之規格要求日益嚴苛，通常需要達到數個微微秒之內，故難以在晶片中產生符合規格之時脈。在這篇論文中，提出了一種適用於消除類比數位轉換器中之抖動誤差的方法。在此種方法中，信號每個取樣點之斜率為一重要的關鍵參數。隨著信號頻率增加，由此演算法所計算出之斜率會開始受到sinc函數的影響而導致失真。此時查表法可以用來補償這種效應，使得系統能操作在接近Nyquist-rate之頻率。
在所提出的架構中，需要一時間數位轉換器來進行數位化抖動誤差消除的演算法。此外，此時間數位轉換器必須擁有較大的動態範圍與高解析度，如此才能涵蓋峰對峰抖動範圍同時維持準確度。在此論文中，設計了一個10微微秒以及5.12奈秒動態範圍之基於倍化式延時鎖定迴路(multiplying DLL)局部被動內插(local passive interpolation)之時間數位轉換器。電路製作使用標準90奈米互補金氧半導體邏輯製程，所設計的時間數位轉換器在1伏特電壓源供應下，功率消耗為6毫瓦。此電路的晶片面積為0.17毫米平方。 | zh_TW |
| dc.description.abstract | The requirement of sampling clock jitter becomes rigorous in the high-speed and high-precision analog-to-digital date conversion, usually around few pico-seconds, which is unreachable for the on-chip clock generation. A method is proposed to cancel the jitter-induced errors in ADC. One of the key parameters needed here is the derivative of each sampled points. The derivative calculated from the algorithm is distorted by a sinc function as the signal frequency gets higher. A look-up table method is applied to compensate the distortion factor which makes the system to operate well near Nyquist rate.
In this architecture, a time-to-digital converter (TDC) is desired to adopt the jitter cancellation algorithm in the digital domain. Besides, this TDC need to be wide dynamic range and high precision in order to cover the peak-to-peak jitter variation while maintain the accuracy. In this thesis, an MDLL-based TDC with local passive interpolation which has 10ps resolution and 5.12ns dynamic range is designed. Fabricated in a 90-nm CMOS technology, the TDC consumes 6.0mW from a 1-V power supply while the active area is only 0.017mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-20T20:03:33Z (GMT). No. of bitstreams: 1 ntu-98-R96943007-1.pdf: 3217906 bytes, checksum: 29cab3ced56576e27309b78d17d96995 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation and Research Goals 1 1.2 Thesis Overview 2 Chapter 2 Basic Concepts and Proposed Jitter Error Cancellation Algorithm 5 2.1 Introduction 5 2.2 Basic Concepts 6 2.2.1 Conventional Jitter Requirement for Nyquist-Rate ADC 6 2.2.2 Generic Autocorrelation Function in the Linear Approximation 6 2.3 Proposed Jitter Error Cancellation Algorithm 8 2.3.1 Jitter Terminology and Measurement 9 2.3.2 Derivative Estimation by Two Points 11 2.3.3 Derivative Estimation by Three Points 12 2.3.4 High Frequency Response Improvement 14 2.4 Summary 16 Chapter 3 Fundamentals of Time-to-Digital Converter 17 3.1 Introduction 17 3.2 TDC Performance Metrics 18 3.2.1 Dynamic Range 18 3.2.2 Conversion Time and Dead Time 18 3.2.3 Single Shot Precision 18 3.2.4 Interpolation Factor 19 3.2.5 Nonlinearity 19 3.3 Architectures of Time-to-Digital Converter 21 3.3.1 Time-to-Voltage-to-Digital Converter 21 3.3.2 Vernier-Based TDC 22 3.3.3 Pulse-Shrinking Cyclic TDC 24 3.3.4 DLL Interpolation TDC 25 3.3.5 Local Passive Interpolation TDC 27 Chapter 4 System Architecture of a MDLL-Based TDC with Local Passive Interpolation 29 4.1 Introduction 29 4.1.1 Multiplying DLL 29 4.1.2 Local Passive Interpolation and Phase Averaging 33 4.2 Architecture of the MDLL-Based TDC with Local Passive Interpolation 36 4.2.1 System Architecture 36 4.2.2 Dynamic Range and Resolution 38 4.3 Summary 41 Chapter 5 Circuit Implementation 43 5.1 Introduction 43 5.2 Architecture 43 5.3 Delay Cell 44 5.4 Phase Frequency Detector 45 5.5 Charge Pump 47 5.6 Divider 48 5.7 Control Logic 49 5.8 Arbiter 50 5.9 Encoder 51 5.10 Output Buffers 52 5.10.1 Digital Output Buffer 52 5.10.2 Open-Drain Output Buffer 53 5.11 Transistor-Level Simulation 53 5.12 Layout and Performance Summary 57 Chapter 6 Test and Experimental Results 59 6.1 Introduction 59 6.2 Chip Die Photo 59 6.3 Test Strategy 60 6.3.1 Test Setup 60 6.3.2 Print Circuit Board Design 61 6.3 Experimental Results 64 Chapter 7 Conclusion 65 7.1 Conclusion 65 Bibliography 67 | |
| dc.language.iso | en | |
| dc.title | 用於類比數位轉換器抖動誤差消除之時間數位轉換器 | zh_TW |
| dc.title | A Time-to-Digital Converter for ADC Jitter Error Cancellation | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Liin),陳信樹(Hsin-Shu Chen),陳巍仁(Wei-Zen Chen) | |
| dc.subject.keyword | 類比數位轉換器,斜率,抖動誤差消除,抖動規格要求,週期抖動,取樣過程,信噪比, | zh_TW |
| dc.subject.keyword | ADC,derivative,jitter error cancellation,jitter requirement,period jitter,sampling process,SNR, | en |
| dc.relation.page | 70 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2009-08-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-98-1.pdf | 3.14 MB | Adobe PDF | 檢視/開啟 |
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