低溫多晶矽製程下基於壓控振盪器的近靜態信號感測 器讀取電路設計

Abstract

本作品呈現了實作於 3 微米低溫多晶矽-薄膜電晶體製程的類比數位轉換器，主要應用於近靜態信號的感測。在類比數位轉換器的設計方面，選用時域操作的架構，解決電晶體嚴重不匹配所引起的電壓偏移，可能會導致電路飽和的問題，使得電路可以正確運作。時域的電路設計上，使用壓控振盪器取代傳統的積分器，以達到面積的高效運用。此外，採用了單端的系統級斬波技術，近一步消除電路貢獻的雜訊，提升整體的解析度和動態範圍。在電路的輸出端加入線性補償的演算法，大幅提升電路的線性度。此晶片的核心面積僅 3.6 mm2，功率消耗為 505 µW (操作在5 V 電源下)，在 0.6 V 的輸入和 250 赫茲的頻寬下，可以達到 48.2 dB 的信噪比。 而最小的輸入端積分等效雜訊為 0.63 mVrms，實現了 59.6 dB 的動態範圍。在品質因素方面分別達到 FoMs = 105.2 dB 及 FoMw = 4.8 nJ/conv.。

In this dissertation, an analog-to-digital converter (ADC) implemented in 3-µm low temperature polycrystalline silicon thin-film transistor (LTPS-TFT) is presented. The primary objective of this work is to develop an ADC that offers high resolution and good energy efficiency for quasi-signal sensing applications. The proposed voltage-controlled oscillator (VCO)-based ADC features an area efficient and digitally intensive architecture for low-voltage operation. By employing time-domain operation, the circuit is able to mitigate issues arising from transistor mismatch and prevent saturation. Additionally, the system-level chopping technique is employed to cancel out offset voltage and flicker noise, resulting in an improved signal to-noise ratio (SNR) and dynamic range (DR). Moreover, a linear compensation method is adopted to improve the overall linearity.The core area of the ADC is 3.6 mm2, and it consumes only 505 µW of power under a 5-V power supply voltage. When operating at full-scale input voltage of 0.6 V, the SNR is measured at 48.2 dB, and the effective number of bits (ENOB) is 7.72 bits. For minimum input voltage of 1 mV and a frequency bandwidth of 250 Hz, the integrated input-referred noise is 0.63 mVrms, resulting in a DR of 59.6 dB. The FoMs of the ADC is 105.2 dB, while the FoMw is 4.8 nJ/conv.