嵌入式多晶片互連橋接封裝技術之平面規劃

Abstract

現今異質整合 (heterogeneous integration) 除了將不同功能及製程的晶片做整合以外，也需要滿足晶片間的高密度連線，以能夠支援需要高頻寬傳輸 (bandwidth) 的晶片設計，例如中央處理器和繪圖處理器與高頻寬記憶體間的高密度連線以及高速資料傳輸。嵌入式多晶片互連橋接封裝技術 (embedded multi-die interconnect bridge, EMIB) 提供局部的高密度佈線結構，且相對於廣泛使用的矽中介層 (silicon interposer)，它具有更加穩定的封裝結構以及可使用較小光罩尺寸而備受關注。然而，多晶片封裝 (multi-chip packaging) 在使用嵌入式多晶片互連橋接上需要考慮物理上的連線限制，串擾及能量消耗。 在這篇論文中，我們提出了第一個在考量嵌入式多晶片互連橋接的多晶片封裝平面規劃演算法。我們提出 B*樹以及遞移封閉圖 (transitive closure graph) 的混合資料結構來去表現平面規劃，並基於此結構制定退火 (simulated annealing) 演算法，以有效率地生成符合嵌入式多晶片互連橋接限制的部分遞移封閉圖拓譜結構。我們進一步採用最大生成樹的分割演算法和樹狀結構的分類機制，透過分析嵌入式多晶片互連橋接的拓譜結構來搜索所需的合法平面規劃。實驗結果顯示，與單獨基於遞移封閉圖的退火相比，我們的演算法可以顯著改善面積，總線長以及運算時間。

Modern heterogeneous integration requires dense IO interconnections between chips, such as CPU and memory, to facilitate bandwidth-aware packaging. The embedded multi-die interconnection bridge (EMIB) has attracted much attention recently by providing a high wiring density and stable package structure with a small reticle size. However, EMIB optimization must consider constrained wire orientations and crosstalk. This paper presents the first work on floorplanning for EMIB-based packaging. We first model the floorplanning problem for EMIB-based packaging. Based on a hybrid structure of transitive closure graphs and B*-trees, we present a novel simulated-annealing-based algorithm to generate the desired EMIB-aware floorplans efficiently. We employ maximum-spanning-tree-based partitioning and tree-based classification for already found partial topologies to search for desired solutions more efficiently. Experimental results show that our algorithm can significantly improve the area, total wirelength, and computation time compared with simulated annealing based on TCGs alone.