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標題: | 3300伏特碳化矽分離閘極金氧半場效電晶體設計 Design of 3300 V 4H-SiC Split Gate MOSFET |
作者: | Hsien-Yi Wu 吳顯逸 |
指導教授: | 李坤彥(Kung-Yen Lee) |
關鍵字: | 碳化矽,金氧半場效電晶體,電流擴散層,特徵導通電阻,崩潰電壓,閘-汲電荷,逆向恢復電容, 4H-SiC,MOSFET,current spreading layer,characteristic on-resistance,breakdown voltage,gate-drain charge,reverse recovery capacitance, |
出版年 : | 2022 |
學位: | 碩士 |
摘要: | 本篇論文透過TCAD Sentaurus軟體進行3300 V 4H-SiC分離閘極金氧半場效電晶體之模擬及優化設計。最終提出分離閘極緩衝金氧半場效電晶體(Split Buffered Gate MOSFET, SBG-MOSFET)以及階梯閘極緩衝金氧半場效電晶體(Terraced Buffered Gate MOSFET, TBG-MOSFET)之結構設計。針對MOSFET中的P型緩衝層以及N型重複磊晶層的濃度進行優化,並在JFET區中加入電流擴散層(Current Spread Layer, CSL)降低元件導通電阻。此兩種不同閘極結構設計與一般平面式結構相比,在維持相同崩潰電壓的前提下,可以獲得更低的特徵導通電阻以及較低閘-汲電荷,意味著元件有著較快的切換速度,較低的能量損耗。優化後的設計可使得特徵導通電阻相較傳統平面式結構約降低53%,在逆向偏壓下,可以維持與傳統平面式結構相近的崩潰電壓3900 V。此外,新穎分離式閘極結構可大幅提高閘極下方氧化層可靠度,相較傳統平面式結構,氧化層崩潰電場因為P型緩衝層結構的保護下較低了約30%。在動態表現上,由於採用分離式閘極結構,使得閘極金屬與JFET區重疊的面積減少進而降低了逆向恢復電容(Reverse Transfer Capacitance, Crss ),切換損耗相較傳統平面式結構減少了57.8%。因此,未來在高頻的切換應用上可有不錯的發展。 In this thesis, TCAD Sentaurus software was used to simulate and optimize the designs of 3300 V 4H-SiC Split gate MOSFET. Finally, the Split Buffered Gate MOSFET (SBG-MOSFET) and the Terraced Buffered Gate MOSFET (TBG-MOSFET) were proposed. The concentration of the P-type buffer layer and the N-type multilayer epitaxial in the MOSFET was optimized, and the current spread layer (CSL) was added to the JFET region to reduce the on-resistance. Compared with the conventional MOSFET, both of structures with different poly gate designs can obtain lower characteristic on-resistance and lower gate-drain charge under the same breakdown voltage, which means that the devices have a faster switching speed and a lower power lost. The optimized design can reduce the characteristic on-resistance by about 53% compared with the conventional MOSFET. For the reverse characteristics, it can withstand a breakdown voltage of 3900 V with a low leakage current. Otherwise, the SBG-MOSFET and TBG-MOSFET can greatly improve the oxide reliability. Compared with the conventional MOSFET, the critical electric field of the oxide is about 30% lower due to the protection of the P-type buffer layer. In terms of dynamic performance, due to the use of the split gate structure, the overlapping area between the gate metal and the JFET region is reduced, which reduces the reverse recovery capacitance (Crss), and the switching loss is reduced by 57.8% compared with the traditional planar structure. . Therefore, there may be a good development in the application of high frequency switching in the future. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84492 |
DOI: | 10.6342/NTU202203988 |
全文授權: | 同意授權(限校園內公開) |
電子全文公開日期: | 2022-09-30 |
顯示於系所單位: | 工程科學及海洋工程學系 |
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U0001-2509202200573400.pdf 授權僅限NTU校內IP使用(校園外請利用VPN校外連線服務) | 9.98 MB | Adobe PDF | 檢視/開啟 |
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