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  1. NTU Theses and Dissertations Repository
  2. 工學院
  3. 工程科學及海洋工程學系
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84492
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor李坤彥(Kung-Yen Lee)
dc.contributor.authorHsien-Yi Wuen
dc.contributor.author吳顯逸zh_TW
dc.date.accessioned2023-03-19T22:13:19Z-
dc.date.copyright2022-09-30
dc.date.issued2022
dc.date.submitted2022-09-25
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Novel trench-etched double-diffused SiC MOS (TED MOS) for overcoming tradeoff between R<inf>on</inf>A and Q<inf>gd</inf>. in 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD). 2015. Baliga, B.J., Fundamentals of power semiconductor devices, 2010. Masuda, T., Kosugi, R., and Hiyoshi, T. 0.97 mΩcm<sup>2</sup>/820 V 4H-SiC super junction V-groove trench MOSFET. in 2016 European Conference on Silicon Carbide & Related Materials (ECSCRM). 2016. Uchida, K., Saitoh, Y., Hiyoshi, T., Masuda, T., Wada, K., Tamaso, H., Hatayama, T., Hiratsuka, K., Tsuno, T., Furumai, M., and Mikamura, Y. The optimised design and characterization of 1200 V / 2.0 mΩ cm<sup>2</sup> 4H-SiC V-groove trench MOSFETs. in 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD). 2015. Harada, S., Kobayashi, Y., Ariyoshi, K., Kojima, T., Senzaki, J., Tanaka, Y., and Okumura, H., 3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET With Reduced Gate Oxide Field. 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Huang, A.Q., New unipolar switching power device figures of merit. IEEE Electron Device Letters, 2004. 25(5): p. 298-301. Cooper, K.T.a.J.A., Fundamentals of Silicon Carbide Technology: Growth Characterization, Vol. vol. 1. 2014. Saha, A. and Cooper, J.A., A 1-kV 4H-SiC Power DMOSFET Optimized for Low <emphasis emphasistype='smcaps'>on</emphasis>-Resistance. IEEE Transactions on Electron Devices, 2007. 54(10): p. 2786-2791. Shengqi, S., Xintian, Z., Ruifeng, Y., and Yan, W. An improved structure of 3.3kV 4H-SiC VDMOSFETs with lower on-resistance and reverse transfer capacitance. in 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). 2016. Zhou, X., Yue, R., Dai, G., Li, J., and Wang, Y. An improved structure to enhance the robustness of SiC power MOSFETs for a low R<inf>on, sp</inf>. in 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). 2016. Tachiki, K., Ono, T., Kobayashi, T., and Kimoto, T., Short-Channel Effects in SiC MOSFETs Based on Analyses of Saturation Drain Current. IEEE Transactions on Electron Devices, 2021. 68(3): p. 1382-1384. Tachiki, K., Ono, T., Kobayashi, T., Tanaka, H., and Kimoto, T., Estimation of Threshold Voltage in SiC Short-Channel MOSFETs. IEEE Transactions on Electron Devices, 2018. 65(7): p. 3077-3080. Mutlu, A.A. and Rahman, M. Two-dimensional analytical model for drain induced barrier lowering (DIBL) in short channel MOSFETs. in Proceedings of the IEEE SoutheastCon 2000. 'Preparing for The New Millennium' (Cat. No.00CH37105). 2000. Quanjun, C., Yimen, Z., and Yuming, Z. An Analytical Model of Drain Induced Barrier Lowering Effect for SiC MESFETs. in Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08). 2008. Zhang, Q.C.J., Duc, J., Hull, B., Young, J., Ryu, S.H., Allen, S., and Palmour, J.W., CIMOSFET: A New MOSFET on SiC with a Superior Ron·Qgd Figure of Merit. Materials Science Forum, 2015. 821-823: p. 765-768. Zhang, Q.J., Wang, G., Doan, H., Ryu, S.H., Hull, B., Young, J., Allen, S., and Palmour, J. Latest results on 1200 V 4H-SiC CIMOSFETs with Rsp, on of 3.9 mΩ·cm2 at 150°C. in 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD). 2015. Cha, K., Yoon, J., and Kim, K., 3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications. Electronics, 2021. 10(6). Han, K., Baliga, B.J., and Sung, W., Split-Gate 1.2-kV 4H-SiC MOSFET: Analysis and Experimental Validation. IEEE Electron Device Letters, 2017. 38(10): p. 1437-1440. Ueda, D., Takagi, H., and Kano, G., A new vertical double diffused MOSFET—The self-aligned terraced-gate MOSFET. IEEE Transactions on Electron Devices, 1984. 31(4): p. 416-420. Wei, J., Zhang, M., Jiang, H., Wang, H., and Chen, K.J., Dynamic Degradation in SiC Trench MOSFET With a Floating p-Shield Revealed With Numerical Simulations. IEEE Transactions on Electron Devices, 2017. 64(6): p. 2592-2598. Wei, J., Zhang, M., Jiang, H., Wang, H., and Chen, K.J. Charge storage effect in SiC trench MOSFET with a floating p-shield and its impact on dynamic performances. in 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD). 2017. Han, K., Baliga, B.J., and Sung, W., A Novel 1.2 kV 4H-SiC Buffered-Gate (BG) MOSFET: Analysis and Experimental Results. IEEE Electron Device Letters, 2018. 39(2): p. 248-251. Ni, W., Wang, X., Xu, M., Li, M., Feng, C., Xiao, H., Jiang, L., Li, W., and Wang, Q., Comparative Study of SiC Planar MOSFETs With Different p-Body Designs. IEEE Transactions on Electron Devices, 2020. 67(3): p. 1071-1076. Ni, W., Wang, X., Xu, M., Wang, Q., Feng, C., Xiao, H., Jiang, L., and Li, W., Study of Asymmetric Cell Structure Tilt Implanted 4H-SiC Trench MOSFET. IEEE Electron Device Letters, 2019. 40(5): p. 698-701. Basler, T., Heer, D., Peters, D., Aichinger, T., and Schoerner, R. Practical Aspects and Body Diode Robustness of a 1200 V SiC Trench MOSFET. in PCIM Europe 2018; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management. 2018. Ahmad, S. and Narayanan, G., Double pulse test based switching characterization of SiC MOSFET, 2017. 319-324. Tu, P., Wang, P., Hu, X., Qi, C., Yin, S., and Zagrodnik, M.A. Analytical evaluation of IGBT turn-on loss with double pulse testing. in 2016 IEEE 11th Conference on Industrial Electronics and Applications (ICIEA). 2016.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84492-
dc.description.abstract本篇論文透過TCAD Sentaurus軟體進行3300 V 4H-SiC分離閘極金氧半場效電晶體之模擬及優化設計。最終提出分離閘極緩衝金氧半場效電晶體(Split Buffered Gate MOSFET, SBG-MOSFET)以及階梯閘極緩衝金氧半場效電晶體(Terraced Buffered Gate MOSFET, TBG-MOSFET)之結構設計。針對MOSFET中的P型緩衝層以及N型重複磊晶層的濃度進行優化,並在JFET區中加入電流擴散層(Current Spread Layer, CSL)降低元件導通電阻。此兩種不同閘極結構設計與一般平面式結構相比,在維持相同崩潰電壓的前提下,可以獲得更低的特徵導通電阻以及較低閘-汲電荷,意味著元件有著較快的切換速度,較低的能量損耗。優化後的設計可使得特徵導通電阻相較傳統平面式結構約降低53%,在逆向偏壓下,可以維持與傳統平面式結構相近的崩潰電壓3900 V。此外,新穎分離式閘極結構可大幅提高閘極下方氧化層可靠度,相較傳統平面式結構,氧化層崩潰電場因為P型緩衝層結構的保護下較低了約30%。在動態表現上,由於採用分離式閘極結構,使得閘極金屬與JFET區重疊的面積減少進而降低了逆向恢復電容(Reverse Transfer Capacitance, Crss ),切換損耗相較傳統平面式結構減少了57.8%。因此,未來在高頻的切換應用上可有不錯的發展。zh_TW
dc.description.abstractIn this thesis, TCAD Sentaurus software was used to simulate and optimize the designs of 3300 V 4H-SiC Split gate MOSFET. Finally, the Split Buffered Gate MOSFET (SBG-MOSFET) and the Terraced Buffered Gate MOSFET (TBG-MOSFET) were proposed. The concentration of the P-type buffer layer and the N-type multilayer epitaxial in the MOSFET was optimized, and the current spread layer (CSL) was added to the JFET region to reduce the on-resistance. Compared with the conventional MOSFET, both of structures with different poly gate designs can obtain lower characteristic on-resistance and lower gate-drain charge under the same breakdown voltage, which means that the devices have a faster switching speed and a lower power lost. The optimized design can reduce the characteristic on-resistance by about 53% compared with the conventional MOSFET. For the reverse characteristics, it can withstand a breakdown voltage of 3900 V with a low leakage current. Otherwise, the SBG-MOSFET and TBG-MOSFET can greatly improve the oxide reliability. Compared with the conventional MOSFET, the critical electric field of the oxide is about 30% lower due to the protection of the P-type buffer layer. In terms of dynamic performance, due to the use of the split gate structure, the overlapping area between the gate metal and the JFET region is reduced, which reduces the reverse recovery capacitance (Crss), and the switching loss is reduced by 57.8% compared with the traditional planar structure. . Therefore, there may be a good development in the application of high frequency switching in the future.en
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Previous issue date: 2022
en
dc.description.tableofcontents致謝 I 摘要 II ABSTRACT III 目錄 IV 圖目錄 V 表目錄 VIII 第一章、緒論 1 1.1 前言 1 1.2 碳化矽材料介紹 2 1.3 研究動機 5 1.4 論文大綱 6 第二章、功率元件結構原理 7 2.1 常見的功率元件種類 7 2.2 垂直型功率金氧半場效電晶體 8 2.2.1 垂直型功率金氧半場效電晶體的結構與製程 10 2.2.2 垂直型功率金氧半場效電晶體的順向導通機制 11 2.2.3 垂直型功率金氧半場效電晶體的逆向崩潰機制 15 第三章、模擬環境 18 3.1 物理模型 18 3.2 模擬方法 20 第四章、3300V SIC MOSFET主動區靜態特性 21 4.1 初始3300V SIC PLANAR MOSFET模擬設計 21 4.2 JFET區的最佳化分析 29 4.3 電流通道的最佳化分析 35 4.4 分離式閘極結構分析 38 4.5 分離式緩衝閘極結構分析 45 4.6 靜態特性整理與分析 64 第五章、3300V SIC MOSFET主動區動態特性 67 5.1 電容特性模擬 67 5.2 雙脈衝測試模擬 73 5.3 動態特性整理與分析 82 第六章、結論與未來展望 84 6.1 結論 84 6.2 未來工作 85 參考文獻 86
dc.language.isozh-TW
dc.title3300伏特碳化矽分離閘極金氧半場效電晶體設計zh_TW
dc.titleDesign of 3300 V 4H-SiC Split Gate MOSFETen
dc.typeThesis
dc.date.schoolyear110-2
dc.description.degree碩士
dc.contributor.oralexamcommittee李佳翰(Jia-Han Lee),蕭惠心(Hui-Hsin Hsiao)
dc.subject.keyword碳化矽,金氧半場效電晶體,電流擴散層,特徵導通電阻,崩潰電壓,閘-汲電荷,逆向恢復電容,zh_TW
dc.subject.keyword4H-SiC,MOSFET,current spreading layer,characteristic on-resistance,breakdown voltage,gate-drain charge,reverse recovery capacitance,en
dc.relation.page89
dc.identifier.doi10.6342/NTU202203988
dc.rights.note同意授權(限校園內公開)
dc.date.accepted2022-09-26
dc.contributor.author-college工學院zh_TW
dc.contributor.author-dept工程科學及海洋工程學研究所zh_TW
dc.date.embargo-lift2022-09-30-
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