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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84398完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
| dc.contributor.author | Chung-Yun Tsai | en |
| dc.contributor.author | 蔡仲耘 | zh_TW |
| dc.date.accessioned | 2023-03-19T22:10:22Z | - |
| dc.date.copyright | 2022-03-07 | |
| dc.date.issued | 2022 | |
| dc.date.submitted | 2022-03-02 | |
| dc.identifier.citation | [1]T. Shibasaki et al., “A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 1–2. [2]T. Shibasaki, et al., “A 56Gb/s NRZ electrical 247mW/lane serial link transceiver in 28nm CMOS”, ISSCC, pp. 64-65, Feb. 2016. [3]P.A. Francese, et al., “A 50Gb/s 1.6pJ/b RX data-path with quarter-rate 3-tap speculative DFE”, IEEE Symp. VLSI Circuits, pp. 267-268, June 2018. [4]D. Schinkel, et al., “A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup and Hold Time,” ISSCC Dig. Tech. Papers, pp. 314–315, Feb. 2007. [5]S. Parikh, et al., “A 32Gb/s Wireline Receiver with a Low-Frequency Equalizer, CTLE and 2-Tap DFE in 28nm CMOS,” ISSCC Dig. Tech. Papers, pp. 28–29, Feb. 2013. [6]K. K. Parhi, “Design of Multigigabit Multiplexer-Loop-Based Decision Feedback Equalizers,” IEEE Trans. on VLSI Systems, vol. 13, no. 4, pp 489–493, Apr. 2005. [7]D. Yoo, et al, 'A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS,' IEEE International Solid- State Circuits Conference - (ISSCC), pp. 126-128, Feb 2019. [8]V. Stojanovic, et al., 'Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver,' IEEE Symp. VLSI Circuits, pp. 348-351, June 2004. [9]J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1571–1580, Sep. 2004. [10]A. Cevrero et al., “29.1 A 64 Gb/s 1.4 pJ/b NRZ optical-receiver datapath in 14 nm CMOS FinFET,” in IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 482–483. [11]J. L. Sonntag and J. Stonick, “A digital clock and data recovery architecture for multi-gigabit/s binary links,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1867–1875, Aug. 2006. [12]H. Miyaoka et al., “A 28-Gb/s 4.5-pJ/bit Transceiver With 1-Tap Decision Feedback Equalizer in 28-nm CMOS,” Asian Solid-State Circuits Conf., pp. 245-248, Nov. 2015. [13]E. Depaoli, et al., 'A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR Transceiver in 28nm FDSOI CMOS,' ISSCC, pp. 110-112, Feb. 2018. [14]E. Depaoli et al., 'A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS,' in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 6-17, Jan. 2019. [15]M. Harwood et al., “A 225mW 28Gb/s SerDes in 40nm CMOS With 13dB of Analog Equalization for 100GBASE-LR4 and Optical Transport Lane 4.4 Applications,” ISSCC Dig. Tech. Papers, pp. 326-327, Feb. 2012. [16]D. Cui, et al., “A Dual 23Gb/s CMOS Transmitter/Receiver Chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK Optical Transmission,” in ISSCC Dig. Tech. Papers, Feb. 2012, pp. 330-331. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/84398 | - |
| dc.description.abstract | 本論文旨在40nm CMOS中演示使用波特率時脈資料恢復電路的56-Gb/s NRZ接收器。 此架構可以共享資料決策和相位檢測的比較器，可以大幅度地減少比較器的數量並且降低晶片整體的功耗，內部電路包括可變增益放大器、連續時間等化器、一抽頭決斷反饋等化器、基於相位內插器之全數位時脈資料恢復電路。 | zh_TW |
| dc.description.abstract | The objective of this thesis is to demonstrate the application of baud-rate clock and data recovery in a 56-Gb/s NRZ receiver with TSMC standard digital 40nm CMOS technology. This architecture can share data decision and phase detection comparators, greatly reduce the number of comparators, power consumption, the internal circuit , including variable gain amplifier, continuous time equalizer, one-tap decision feedback equalizer, and all digital clock data recovery circuit based on phase interpolator. | en |
| dc.description.provenance | Made available in DSpace on 2023-03-19T22:10:22Z (GMT). No. of bitstreams: 1 U0001-0203202213293900.pdf: 2610405 bytes, checksum: 0aa5c24beff98abafcca284657eafc91 (MD5) Previous issue date: 2022 | en |
| dc.description.tableofcontents | 口試委員會審定書 # 中文摘要 i ABSTRACT ii CONTENTS iii LIST OF FIGURES v LIST OF TABLES vii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 1 Chapter 2 Introduction of the OIF-CEI-56G 3 2.1 OIF-CEI-56G 3 Chapter 3 A 56-Gb/s NRZ Receiver circuit 5 3.1 Architecture and Building Blocks 5 3.2 Front-end Circuit 6 3.2.1 Variable gain amplifier: 6 3.2.2 Low frequency equalizer: 7 3.2.3 Continuous time linear equalizer: 10 3.3 Decision Feedback Equalizer and Slicer 15 3.3.1 Decision feedback equalizer: 15 3.3.2 Slicer: 17 3.4 Clock and Data Recovery Circuit 19 3.4.1 Phase Detector: 20 3.4.2 Majority Voter: 22 3.4.3 Linearized Model of All digital CDR: 23 Chapter 4 Measurement Results 26 4.1 Measurement Setup 26 4.2 Measurement Results 28 Chapter 5 Conclusions 32 REFERENCE 33 LIST OF FIGURES Fig. 2.1: Application space of 56Gb/s links. 4 Fig. 3.1: 56 Gb/s NRZ receiver architecture. 5 Fig. 3.2: Variable gain amplifier. 6 Fig. 3.3: Low frequency equalizer.. 7 Fig. 3.4: Tuning LFEQ boosting value with (a) Vctrl1, (b) Vctrl2. 8 Fig. 3.5: Ac response of analog front end with LFEQ and without LFEQ.. 9 Fig. 3.6: Eye diagram of analog front end (a) with LFEQ, (b) without LFEQ. 9 Fig. 3.7: (a) Ac response of Keysight M8049A ISI channel , (b) single pulse response. 10 Fig. 3.8: (a) Filter stage with capacitance degeneration, (b) ac response. 11 Fig. 3.9: CTLE which is adjusted R and C. 12 Fig. 3.10: Tuning CTLE boosting value with (a) R degeneration (b) C degeneration. 13 Fig. 3.11: Analog front end (a) ac response, (b) single bit response 14 Fig. 3.12: Eye diagram (a) TT, (b) FF, (c) SS 14 Fig. 3.13: (a) direct feedback DFE, (b) loop unroll DFE. 15 Fig. 3.14: (a) Original loop unroll DFE, (b) Pipeline (look ahead) DFE. 17 Fig. 3.15: (a) Double tail latch, (b) signal behavior. 18 Fig. 3.16: (a) SR latch, (b) truth table 19 Fig. 3.17: All digital PI based CDR block diagram. 20 Fig. 3.18: VLSI2014 Shibasaki's proposed PD logic. 21 Fig. 3.19: (a) FIR boxcar filter, (b) majority voter. 23 Fig. 3.20: The linear model of digital CDR in z domain. 25 Fig. 4.1: 56 Gb/s NRZ receiver layout floorplan. 26 Fig. 4.2: The chip on board setting of 56 Gb/s NRZ receiver. 27 Fig. 4.3: LabVIEW control panel. 27 Fig. 4.4: Measurement setup. 28 Fig. 4.5: The relationship between power and frequency. 29 Fig. 4.6: Poly Phase Filter transfer function. 29 Fig. 4.7: Bathtub @32Gb/s NRZ. 30 Fig. 4.8: Jitter tolerance of CDR at 32Gb/s. 30 LIST OF TABLES Table 4.1: Comparison table. 65 | |
| dc.language.iso | zh-TW | |
| dc.subject | 相位內插器 | zh_TW |
| dc.subject | 連續時間等化器 | zh_TW |
| dc.subject | 波特率相位偵測器 | zh_TW |
| dc.subject | 全數位式時脈資料恢復器 | zh_TW |
| dc.subject | 決策反饋等化器 | zh_TW |
| dc.subject | 可變增益放大器 | zh_TW |
| dc.subject | all digital clock and data recovery | en |
| dc.subject | variable gain amplifier | en |
| dc.subject | low frequency equalizer | en |
| dc.subject | continuous time linear equalizer | en |
| dc.subject | decision feedback equalizer | en |
| dc.subject | baud rate phase detector | en |
| dc.title | 56-Gb/s 不歸零碼接收器 | zh_TW |
| dc.title | 56-Gb/s NRZ Receiver | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 110-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 彭朋瑞(Pen-Jui Peng) | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),曹恆偉(Hen-Wai Tsao) | |
| dc.subject.keyword | 可變增益放大器,連續時間等化器,決策反饋等化器,波特率相位偵測器,相位內插器,全數位式時脈資料恢復器, | zh_TW |
| dc.subject.keyword | variable gain amplifier,low frequency equalizer,continuous time linear equalizer,decision feedback equalizer,baud rate phase detector,all digital clock and data recovery, | en |
| dc.relation.page | 35 | |
| dc.identifier.doi | 10.6342/NTU202200611 | |
| dc.rights.note | 同意授權(限校園內公開) | |
| dc.date.accepted | 2022-03-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| dc.date.embargo-lift | 2022-03-07 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
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