DC-DC 轉換器之進階恆定導通時間控制系統

Abstract

近年來隨著手持式裝置與電腦設備需求遽增，對於電源管理式晶片之要求也越來越嚴苛。如何設計出具有大功率密度、快速動態響應、廣泛輸入輸出範圍等優點，為現今開發電源管理式晶片所追尋的目標，而本論文將針對兩種不同的直流壓降式電路進行探討。 第一種架構主要針對漣波控制固定導通時間壓降轉換器進行實驗。實作方式為參考既有之架構，利用文獻中提及之小訊號模型進行模擬，並於回授路徑中，加入解決穩定度並改善抽載暫態響應的技巧。當抽載暫態響應發生時，其輸出電壓下降不超過50豪伏特/安培，並於低抽載時進入不連續導通模式，降低切換所耗，晶片使用台積電180奈米製程，尺寸為1.2×1.0平方毫米，最高效率為83.4%。 第二種架構改善了時間電荷控制法實現時域式降壓轉換器，此架構支援大範圍的輸入與輸出電壓，並可在不同操作範圍下維持固定的品質因子，以維持系統穩定性。本次實驗透過堆疊式電容實現被動元件，使晶片面積有效下降，並利用輸出電壓回授，使低抽載時能完成不連續導通模式，並有效降頻，完成高功率密度之設計。由於高增益電壓回授路徑，使電路整體之電源電壓調整率及負載調整率各自小於1毫伏特/伏特及1毫伏特/安培，晶片使用台積電180奈米製程，尺寸為0.9×1.1平方毫米，最高效率為94.9%。

With the strong demand for handheld devices and computer equipment in recent years, the requirements for power management ICs are becoming more and more stringent. The design of power management ICs with high power density, fast dynamic response, and wide input and output range are the main goals of today's power management IC development. Two different types of DC-DC converters are discussed in this thesis. The first architecture focuses on a ripple-based constant on-time buck converter. The purpose is to solve the stability problem and to improve the load transient response by analyzing the small signal model mentioned in the reference. A proposed technique applying to the feedback path is the main research content in this work. The converter can regulate the output voltage with less than 50 mV/A undershoot/overshoot when the load transient occurs. The converter with discontinuous conduction mode (DCM) condition can reduce the switching loss at light load condition. The chip is fabricated in TSMC 180-nm CMOS process and occupies 1.2 x 1.0 mm2. Peak efficiency is 83.4%. The second architecture improves a time-charge-based control buck converter, which has a fixed quality factors to maintain system stability under wide input and output operation range. In this work, the passive components are implemented by stacked capacitors to reduce the chip area. The feedback output voltage is used to realize the DCM operation at light load condition. Owing to the above two reasons, a high power density design can be achieved. Due to the high-gain voltage loop, the line regulation and the load regulation of the circuit are less than 1 mV/V and 1 mV/A respectively. The chip is fabricated in TSMC 180-nm CMOS process and occupies 0.9×1.1 mm2. Peak efficiency is 94.9%.