應用於LTE-20MHz無線通訊傳輸功率放大器之混合式封包追蹤電源調變器設計

Abstract

隨著全球通訊的演進，如今的通訊協定已發展到了第五代。射頻傳輸訊號的通道頻寬及峰均功率比等規格皆不斷上升，因此功率放大器之效率逐漸成為一項重要的議題，封包追蹤技術可根據射頻訊號之封包來動態調整提供給功率放大器之供應電壓，相較於傳統高準位的固定電壓，能提升功率放大器之轉換效率。 對於封包追蹤轉換器的系統而言，電路所採用的架構會顯著的影響整體的性能。為了同時達到良好的轉換效率以及準確的訊號追蹤能力，本研究採用並聯組合架構，主要由一線性放大器與一切換放大器所組成，前者擁有高頻訊號之追蹤能力，並具備用以壓抑雜訊之低輸出阻抗；後者則可輸出直流功率並維持高效率。線性放大器整體由一個軌對軌輸入之摺疊疊接運算放大器搭配浮動電流源控制的Class-AB輸出級所組成，另外此電路也利用定轉導偏壓電路以保持線性放大器對於各項變異的低敏感度；切換放大器則使用一加入了電阻、電容補償之遲滯比較器，可以有效的降低比較時間延遲，達到較快之控制迴路速度。除此之外在前端電流感測的部份加入一轉導放大器解決Class-AB電流鏡的通道調變效應，同時也提升整體電流迴路的速度。 本晶片實作於台積電180奈米之CMOS製程。電路部分使用3.3伏特的高壓元件以提供3.5伏特之供應電壓。另外，此晶片之整體面積包含pad為0.875平方毫米。當測量電源轉換器本身之效能，負載端可由被動元件替代功率放大器。此時系統量測到之峰值效率為83.96%。而於測量封包追蹤功率放大器整體系統性能方面，其傳輸效率於最大輸出功率下可從11.44%改善至30.59%，相鄰頻道洩漏比則為-53.63 dBc。

With the evolution of global communication, the protocol has been developed to the 5th generation. Specifications such as channel bandwidth and peak-to-average power ratio (PAPR) of RF transmission signals are constantly rising. Therefore, the efficiency of a power amplifiers (PA) has gradually become an important issue. The envelope tracking technique dynamically adjust the supply voltage of the power amplifier based on the input RF signal, which can provide a higher conversion efficiency when compared to traditional fixed-supply topology. For the envelope tracking supply modulator (ETSM) system, the circuit architecture being adopted will highly influence the total performance. In order to obtain high efficiency while maintaining accurate signal tracking ability, a parallel-connected topology is adopted in this thesis. It consists of a linear amplifier (LA) and a switching amplifier (SA). The former is capable of wideband envelope signal tracking while possessing low output impedance for noise suppression, and the latter is responsible for providing most of the power to the output with high efficiency. The LA consists of a rail-to-rail input folded-cascode amplifier and a floating-current-source-controlled Class-AB output stage. Furthermore, a constant-gm bias circuit is added to maintain low sensitivity toward variations. The SA employs a hysteresis comparator with RC compensation for less time delay, and thus achieving faster control loop speed. In addition, a transimpedance amplifier (TIA) is inserted in front of the hysteresis comparator to manage the effect of channel-length modulation and enhance the control loop response at the same time. The chip is fabricated in TSMC 0.18-um CMOS process with 3.3-V high-voltage devices for 3.5-V supply voltage and the total occupied area including I/O pads is 0.875-mm2. For measuring the performance of ETSM itself, the PA can be replaced by passive elements. In this case, the measured peak efficiency reaches 83.96%. Considering the performance of the ETPA system, the transmission efficiency is improved from 11.44% to 30.59% at the maximum output power while the adjacent channel leakage ratio (ACLR) of the output spectrum is -53.63 dBc.