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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83114
標題: | 數位化且以延遲鎖定迴路為基底的小數型頻率合成器 A Digital DLL-based Fractional-N Frequency Synthesizer |
其他標題: | A Digital DLL-based Fractional-N Frequency Synthesizer |
作者: | 洪麒麟 CI-LIN HONG |
指導教授: | 陳中平 Chung-Ping Chen |
關鍵字: | 延遲鎖定迴路,小數型頻率合成器,小面積,相位雜訊,無條件穩定, Delay-Locked Loop,Fractional-N Frequency Synthesizer,Small Area,Phase Noise,Unconditional Stability, |
出版年 : | 2022 |
學位: | 碩士 |
摘要: | 我們提出了一個小數型頻率合成器,採用DLL-based的架構,可以讓我們有更佳的輸出抖動表現,此外,由於採用DLL-based的架構,我們不必擔心系統穩定度的問題。另一方面,採用數位化的子電路可以節省大量的面積,由於儲存資訊的類比電容可以被面積小的計數器取代,而且,採用數位化的實現方式,可以使得整體系統對PVT變動更不敏感。數位化的實現方式還能提供一個優點,就是已經設計好的系統可以很容易地轉移到先進的製程節點,也就是說,可以節省大量的成本及時間。
此架構能實現小數型的頻率合成,原理在於,我們可以根據不同的倍頻倍數來調整延遲線的總長度,此外,為了降低面積,我們的延遲線可以由控制器改變其拓樸,我們可以透過讓延遲線變為閉迴路的方式,重複使用,因此我們可以用有限的布局面積,卻獲得和非常長的延遲線等同的效果。 本晶片使用台積電90奈米互補式金氧半製程,主動區域面積約0.007mm2,給定供應電壓為1.1V,且參考時脈為頻率25MHz,當輸出頻率為621.875MHz時,在偏移輸出頻率1MHz的相位雜訊為 -92 dBc/Hz,方均根抖動為15.8ps,消耗功率為0.83mW。 We propose a Fractional-N frequency synthesizer with a DLL-based architecture, which allows us to have better output jitter performance. In addition, due to the DLL-based architecture, we don't have to worry about system stability. On the other hand, the use of digitized sub-circuits can save a lot of areas, because the analog capacitors that store information can be replaced by counters, and the use of digitized implementations can make the overall system less sensitive to PVT variations. The digital implementation also offers the advantage that already designed systems can be easily transferred to advanced process nodes, that is, significant cost and time can be saved. This architecture can realize Fractional-N frequency synthesis. The principle is that we can adjust the total length of the delay line according to different frequency multipliers. In addition, in order to reduce the area, the topology of the delay line can be changed by the controller. By making the delay line a closed loop, delay cells can be reused, so we can get the same effect as a very long delay line with a limited layout area. This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.007mm2. The given reference signal frequency is 25MHz and the supply voltage is 1.1V. When the output frequency is 621.875MHz, the power consumption is 0.83mW, the phase noise is -92 dBc/Hz at 1MHz offset, and the RMS jitter is 15.8ps. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/83114 |
DOI: | 10.6342/NTU202210063 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
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U0001-0401221118223138.pdf | 10.51 MB | Adobe PDF | 檢視/開啟 |
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