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請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/79729
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor吳育任(Yuh-Renn Wu)
dc.contributor.authorPin-Fang Chenen
dc.contributor.author陳品方zh_TW
dc.date.accessioned2022-11-23T09:09:03Z-
dc.date.available2021-09-02
dc.date.available2022-11-23T09:09:03Z-
dc.date.copyright2021-09-02
dc.date.issued2021
dc.date.submitted2021-08-24
dc.identifier.citationL. Yang, K. Majumdar, Y. Du, H. Liu, H. Wu, M. Hatzistergos, P. Hung, R. Tieckelmann, W. Tsai, C. Hobbs et al., “High-performance MoS 2 fieldeffect transistors enabled by chloride doping: Record low contact resistance (0.5 ku μm) and record high drain current (460 μA/μm),” in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers. IEEE, 2014, pp. 1–2. vii, 9 M.-C. Chen, K.-S. Li, L.-J. Li, A.-Y. Lu, M.-Y. Li, Y.-H. Chang, C.-H. Lin, Y.-J. Chen, Y.-F. Hou, C.-C. Chen et al., “TMD FinFET with 4 nm thin body and back gate control for future low power technology,” in 2015 IEEE International Electron Devices Meeting (IEDM). IEEE, 2015, pp. 32–2. vii, 9 A. Nourbakhsh, A. Zubair, A. Tavakkoli, R. Sajjad, X. Ling, M. Dresselhaus, J. Kong, K. Berggren, D. Antoniadis, and T. Palacios, “Serially connected monolayer MoS 2 FETs with channel patterned by a 7.5 nm resolution directed self-assembly lithography,” in 2016 IEEE Symposium on VLSI Technology. IEEE, 2016, pp. 1–2. vii, 9 S. Park and D. Akinwande, “First demonstration of high performance 2D monolayer transistors on paper substrates,” in 2017 IEEE International Electron Devices Meeting (IEDM). IEEE, 2017, pp. 5–2. vii, 4, 9 C. Huyghebaert, T. Schram, Q. Smets, T. K. Agarwal, D. Verreck, S. Brems, A. Phommahaxay, D. Chiappe, S. El Kazzi, C. L. De La Rosa et al., “2D materials: roadmap to CMOS integration,” in 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018, pp. 22–1. vii, 9 Q. Smets, G. Arutchelvan, J. Jussot, D. Verreck, I. Asselberghs, A. N. Mehta, A. Gaur, D. Lin, S. El Kazzi, B. Groven et al., “Ultra-scaled MOCVD MoS 2 MOSFETs with 42nm contact pitch and 250μA/μm drain current,” in 2019 IEEE International Electron Devices Meeting (IEDM). IEEE, 2019, pp. 23–2. vii, 9 A. S. Chou, P. C. Shen, C. C. Cheng, L. S. Lu, W. C. Chueh, M. Y. Li, G. Pitner, W. H. Chang, C. I. Wu, J. Kong et al., “High On-Current 2D nFET of 390\mu A/\mu m at VDS= 1V using Monolayer CVD MoS2 without Intentional Doping,” in 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020. Institute of Electrical and Electronics Engineers Inc., 2020, p. 9265040. vii, 9 Y.-Y. Chung, K.-C. Lu, C.-C. Cheng, M.-Y. Li, C.-T. Lin, C.-F. Li, J.-H. Chen, T.-Y. Lai, K.-S. Li, J.-M. Shieh et al., “Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS 2 Channel Directly Grown on SiO2/Si Substrates Using Area-Selective CVD Technology,” IEEE Transactions on Electron Devices, vol. 66, no. 12, pp. 5381–5386, 2019. vii, 9 C.-S. Pang, P. Wu, J. Appenzeller, and Z. Chen, “Sub-1nm EOT WS 2-FET with I DS¿ 600μA/μm at V DS= 1V and SS¡ 70mV/dec at L G= 40nm,” in 2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 2020, pp. 3–4. vii, 9, 50 D. Lin, X. Wu, D. Cott, D. Verreck, B. Groven, S. Sergeant, Q. Smets, S. Sutar, I. Asselberghs, and I. Radu, “Dual gate synthetic WS 2 MOSFETs with 120μS/μm Gm 2.7 μF/cm 2 capacitance and ambipolar channel,” in 2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 2020, pp. 3–6. vii, 9 “2020 IRDS roadmap,” 2020. vii, xiv, 12, 13 S.-H. Lo, D. Buchanan, Y. Taur, and W. Wang, “Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s,” IEEE Electron Device Letters, vol. 18, no. 5, pp. 209–211, 1997. x, 46, 47 S. Guha, E. Cartier, N. Bojarczuk, J. Bruley, L. Gignac, and J. Karasinski, “High-quality aluminum oxide gate dielectrics by ultra-high-vacuum reactive atomic-beam deposition,” Journal of applied physics, vol. 90, no. 1, pp. 512–514, 2001. x, 46, 47 E. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. Jamison, D. Neumayer et al., “Ultrathin high-K gate stacks for advanced CMOS devices,” in International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224). IEEE, 2001, pp. 20–1. x, 46, 47 L. Britnell, R. V. Gorbachev, R. Jalil, B. D. Belle, F. Schedin, M. I. Katsnelson, L. Eaves, S. V. Morozov, A. S. Mayorov, N. M. Peres et al., “Electron tunneling through ultrathin boron nitride crystalline barriers,” Nano letters, vol. 12, no. 3, pp. 1707–1710, 2012. x, 46, 47 C.-Y. Huang, G. Dewey, E. Mannebach, A. Phan, P. Morrow, W. Rachmady, I.-C. Tung, N. Thomas, U. Alaan, R. Paul et al., “3-D Self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore’s law scaling,” in 2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 2020, pp. 20–6. xiii, 11, 61, 62 R. Ritzenthaler, H. Mertens, V. Pena, G. Santoro, A. Chasin, K. Kenis, K. Devriendt, G. Mannaert, H. Dekkers, A. Dangol et al., “Vertically stacked gateall-around Si nanowire CMOS transistors with reduced vertical nanowires separation, new work function metal gate solutions, and DC/AC performance optimization,” in 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018, pp. 21–5. xiii, 61, 62 S.-G. Hur, J.-G. Yang, S.-S. Kim, D.-K. Lee, T. An, K.-J. Nam, S.-J. Kim, Z. Wu, W. Lee, U. Kwon et al., “A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies,” in 2013 IEEE international electron devices meeting. IEEE, 2013, pp. 26–5. xiii, 61, 62 H. Mertens, R. Ritzenthaler, A. Hikavyy, M.-S. Kim, Z. Tao, K. Wostyn, S. A. Chew, A. De Keersgieter, G. Mannaert, E. Rosseel et al., “Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates,” in 2016 IEEE Symposium on VLSI Technology. IEEE, 2016, pp. 1–2. xiii, 61, 62 H. Mertens, R. Ritzenthaler, A. Chasin, T. Schram, E. Kunnen, A. Hikavyy, L.-A. Ragnarsson, H. Dekkers, T. Hopf, K. Wostyn ˚ et al., “Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates,” in 2016 IEEE International Electron Devices Meeting (IEDM). IEEE, 2016, pp. 19–7. xv, 61, 62 S. Barraud, B. Previtali, C. Vizioz, J.-M. Hartmann, J. Sturm, J. Lassarre, C. Perrot, P. Rodriguez, V. Loup, A. Magalhaes-Lucas et al., “7-levels-stacked nanosheet GAA transistors for high performance computing,” in 2020 IEEE Symposium on VLSI Technology. IEEE, 2020, pp. 1–2. xiii, 61, 62 S. Bangsaruntip, K. Balakrishnan, S.-L. Cheng, J. Chang, M. Brink, I. Lauer, R. Bruce, S. Engelmann, A. Pyzyna, G. Cohen et al., “Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond,” in 2013 IEEE international electron devices meeting. IEEE, 2013, pp. 20–2. xiii, 61, 62 I. Lauer, N. Loubet, S. Kim, J. Ott, S. Mignot, R. Venigalla, T. Yamashita, T. Standaert, J. Faltermeier, V. Basker et al., “Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance,” in 2015 Symposium on VLSI Technology (VLSI Technology). IEEE, 2015, pp. T140–T141. xiii, 61, 62 A. Veloso, G. Hellings, M. J. Cho, E. Simoen, K. Devriendt, V. Paraschiv, E. Vecchio, Z. Tao, J. Versluijs, L. Souriau et al., “Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS,” in 2015 Symposium on VLSI Technology (VLSI Technology). IEEE, 2015, pp. T138–T139. xiii, 61, 62 P. Nguyen, S. Barraud, C. Tabone, L. Gaben, M. Cass´e, F. Glowacki, J.-M. Hartmann, M.-P. Samson, V. Maffini-Alvaro, C. Vizioz et al., “Dualchannel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length,” in 2014 IEEE International Electron Devices Meeting. IEEE, 2014, pp. 16–2. xiii, 61, 62 K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, and A. A. Firsov, “Electric field effect in atomically thin carbon films,” science, vol. 306, no. 5696, pp. 666–669, 2004. 1 H. Sun, X. Liu, Y. Su, B. Deng, H. Peng, S. Decurtins, S. Sanvito, S.-X. Liu, S. Hou, and J. Liao, “Dirac-cone induced gating enhancement in single molecule field-effect transistors,” Nanoscale, vol. 11, no. 27, pp. 13 117–13 125, 2019. 1 T. Kim, S. Fan, S. Lee, M.-K. Joo, and Y. H. Lee, “High-mobility junction field-effect transistor via graphene/MoS 2 heterointerface,” Scientific reports, vol. 10, no. 1, pp. 1–8, 2020. 1 F. Bonaccorso, Z. Sun, T. Hasan, and A. Ferrari, “Graphene photonics and optoelectronics,” Nature photonics, vol. 4, no. 9, p. 611, 2010. 1 A. Chaves, J. Azadani, H. Alsalman, D. R. da Costa, R. Frisenda, A. Chaves, S. H. Song, Y. Kim, D. He, J. Zhou et al., “Bandgap engineering of twodimensional semiconductor materials,” npj 2D Materials and Applications, vol. 4, no. 1, pp. 1–21, 2020. 2 P. Zhao, S. Desai, M. Tosun, T. Roy, H. Fang, A. Sachid, M. Amani, C. Hu, and A. Javey, “2D layered materials: From materials properties to device applications,” in 2015 IEEE International Electron Devices Meeting (IEDM). IEEE, 2015, pp. 27–3. 2 T. Mueller and E. Malic, “Exciton physics and device application of twodimensional transition metal dichalcogenide semiconductors,” npj 2D Materials and Applications, vol. 2, no. 1, pp. 1–12, 2018. 2 S.-F. Chen and Y.-R.Wu, “A design of intermediate band solar cell for photon ratchet with multi-layer MoS2 nanoribbons,” Applied Physics Letters, vol. 110, no. 20, p. 201109, 2017. 2 M. Donarelli and L. Ottaviano, “2D materials for gas sensing applications: A review on graphene oxide, MoS2, WS2 and phosphorene,” Sensors, vol. 18, no. 11, p. 3638, 2018. 2 N. Huo, Y. Yang, and J. Li, “Optoelectronics based on 2D TMDs and heterostructures,” Journal of Semiconductors, vol. 38, no. 3, p. 031002, 2017. 2, 3 N. Huo, S. Yang, Z. Wei, S.-S. Li, J.-B. Xia, and J. Li, “Photoresponsive and gas sensing field-effect transistors based on multilayer WS 2 nanoflakes,” Scientific reports, vol. 4, p. 5209, 2014. 2 H. Liu, A. T. Neal, and P. D. Ye, “Channel length scaling of MoS2 MOSFETs,” ACS nano, vol. 6, no. 10, pp. 8563–8569, 2012. 3, 7 S. B. Desai, S. R. Madhvapathy, A. B. Sachid, J. P. Llinas, Q. Wang, G. H. Ahn, G. Pitner, M. J. Kim, J. Bokor, C. Hu et al., “Mos2 transistors with 1-nanometer gate lengths,” Science, vol. 354, no. 6308, pp. 99–102, 2016. 3 A. Nourbakhsh, A. Zubair, R. N. Sajjad, A. Tavakkoli KG, W. Chen, S. Fang, X. Ling, J. Kong, M. S. Dresselhaus, E. Kaxiras et al., “MoS2 field-effect transistor with sub-10 nm channel length,” Nano letters, vol. 16, no. 12, pp.7798–7806, 2016. 3 Z. Yu, H. Wang, W. Li, S. Xu, X. Song, S. Wang, P. Wang, P. Zhou, Y. Shi, Y. Chai et al., “Negative capacitance 2D MoS 2 transistors with sub-60mV/dec subthreshold swing over 6 orders, 250 μA/μm current density, and nearly-hysteresis-free,” in 2017 IEEE International Electron Devices Meeting (IEDM). IEEE, 2017, pp. 23–6. 3, 4 C.-H. Wang, C. McClellan, Y. Shi, X. Zheng, V. Chen, M. Lanza, E. Pop, and H.-S. P. Wong, “3D monolithic stacked 1T1R cells using monolayer MoS 2 FET and hBN RRAM fabricated at low (150 C) temperature,” in 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018, pp. 22–5. 4 R. Yang, H. Li, K. K. Smithe, T. R. Kim, K. Okabe, E. Pop, J. A. Fan, and H.-S. P. Wong, “2D molybdenum disulfide (MoS 2) transistors driving RRAMs with 1T1R configuration,” in 2017 IEEE International Electron Devices Meeting (IEDM). IEEE, 2017, pp. 19–5. 4 J. Li, J. Li, Y. Ding, C. Liu, X. Hou, H. Chen, Y. Xiong, D. W. Zhang, Y. Chai, and P. Zhou, “Highly Area-Efficient Low-Power SRAM Cell with 2 Transistors and 2 Resistors,” in 2019 IEEE International Electron Devices Meeting (IEDM). IEEE, 2019, pp. 23–3. 4 P. Sol´ıs-Fern´andez, M. Bissett, and H. Ago, “Synthesis, structure and applications of graphene-based 2D heterostructures,” Chemical Society Reviews, vol. 46, no. 15, pp. 4572–4613, 2017. 5 T. Kim, S. Fan, S. Lee, M.-K. Joo, and Y. H. Lee, “High-mobility junction field-effect transistor via graphene/MoS 2 heterointerface,” Scientific reports, vol. 10, no. 1, pp. 1–8, 2020. 5 Y. Huang, E. Sutter, N. N. Shi, J. Zheng, T. Yang, D. Englund, H.-J. Gao, and P. Sutter, “Reliable exfoliation of large-area high-quality flakes of graphene and other two-dimensional materials,” ACS nano, vol. 9, no. 11, pp. 10 612–10 620, 2015. 5 P.-C. Shen, Y. Lin, H. Wang, J.-H. Park, W. S. Leong, A.-Y. Lu, T. Palacios, and J. Kong, “CVD technology for 2-D materials,” IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4040–4052, 2018. 5 K.-K. Liu, W. Zhang, Y.-H. Lee, Y.-C. Lin, M.-T. Chang, C.-Y. Su, C.-S. Chang, H. Li, Y. Shi, H. Zhang et al., “Growth of large-area and highly crystalline MoS2 thin layers on insulating substrates,” Nano letters, vol. 12, no. 3, pp. 1538–1544, 2012. 6 Y. Zhan, Z. Liu, S. Najmaei, P. M. Ajayan, and J. Lou, “Large-area vaporphase growth and characterization of MoS2 atomic layers on a SiO2 substrate,” Small, vol. 8, no. 7, pp. 966–971, 2012. 6 C. Lan, Z. Zhou, Z. Zhou, C. Li, L. Shu, L. Shen, D. Li, R. Dong, S. Yip, and J. C. Ho, “Wafer-scale synthesis of monolayer WS 2 for high-performance flexible photodetectors by enhanced chemical vapor deposition,” Nano Research, vol. 11, no. 6, pp. 3371–3384, 2018. 6 H. Xu, H. Zhang, Z. Guo, Y. Shan, S. Wu, J. Wang, W. Hu, H. Liu, Z. Sun, C. Luo et al., “High-performance wafer-scale MoS2 transistors toward practical application,” Small, vol. 14, no. 48, p. 1803465, 2018. 6, 7 Z. Jin, X. Li, J. T. Mullen, and K. W. Kim, “Intrinsic transport properties of electrons and holes in monolayer transition-metal dichalcogenides,” Physical Review B, vol. 90, no. 4, p. 045422, 2014. 6, 7, 35, 86 X. Li, J. T. Mullen, Z. Jin, K. M. Borysenko, M. B. Nardelli, and K. W. Kim, “Intrinsic electrical transport properties of monolayer silicene and MoS 2 from first principles,” Physical Review B, vol. 87, no. 11, p. 115418, 2013. 7, 17 T. Sohier, D. Campi, N. Marzari, and M. Gibertini, “Mobility of twodimensional materials from first principles in an accurate and automated framework,” Physical Review Materials, vol. 2, no. 11, p. 114010, 2018. 7 E. Pascual, J. M. Iglesias, M. J. Mart´ın, and R. Rengel, “Electronic transport and noise characterization in MoS2,” Semiconductor Science and Technology, vol. 35, no. 5, p. 055021, 2020. 7 A. T. Neal, H. Liu, J. Gu, and P. D. Ye, “Magneto-transport in MoS2: phase coherence, spin–orbit scattering, and the hall factor,” Acs Nano, vol. 7, no. 8, pp. 7077–7082, 2013. 7 M. Hosseini, M. Elahi, M. Pourfath, and D. Esseni, “Strain induced mobility modulation in single-layer MoS2,” Journal of Physics D: Applied Physics, vol. 48, no. 37, p. 375104, 2015. 7 Y. Lee, S. Fiore, and M. Luisier, “Ab initio mobility of single-layer MoS 2 and WS 2: comparison to experiments and impact on the device characteristics,” in 2019 IEEE International Electron Devices Meeting (IEDM). IEEE, 2019, pp. 24–4. 7 Z. Yu, Y. Zhu, W. Li, Y. Shi, G. Zhang, Y. Chai, and X. Wang, “Toward High-mobility and Low-power 2D MoS 2 Field-effect Transistors,” in 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018, pp. 22–4. 7 G. Gaddemane, S. Gopalan, M. L. Van de Put, and M. V. Fischetti, “Limitations of ab initio methods to predict the electronic-transport properties of two-dimensional semiconductors: the computational example of 2H-phase transition metal dichalcogenides,” Journal of Computational Electronics, vol. 20, no. 1, pp. 49–59, 2021. 7 D. Braga, I. Gutierrez Lezama, H. Berger, and A. F. Morpurgo, “Highperformance monolayer WS2 field-effect transistors on high-_ dielectrics,” Nano letters, vol. 12, no. 10, pp. 5218–5223, 2012. 7 S. Jo, N. Ubrig, H. Berger, A. B. Kuzmenko, and A. F. Morpurgo, “Monoand bilayer WS2 light-emitting transistors,” Nano letters, vol. 14, no. 4, pp. 2019–2025, 2014. 7 Y. Cui, R. Xin, Z. Yu, Y. Pan, Z.-Y. Ong, X. Wei, J. Wang, H. Nan, Z. Ni, Y. Wu et al., “High-performance monolayer WS2 field-effect transistors on high-_ dielectrics,” Advanced Materials, vol. 27, no. 35, pp. 5230–5234, 2015. 7 J. Singh, Electronic and optoelectronic properties of semiconductor structures. Cambridge University Press, 2007. 7, 22 N. Ma and D. Jena, “Charge scattering and mobility in atomically thin semiconductors,” Physical Review X, vol. 4, no. 1, p. 011043, 2014. 8 N. Loubet, T. Hook, P. Montanini, C.-W. Yeung, S. Kanakasabapathy, M. Guillom, T. Yamashita, J. Zhang, X. Miao, J. Wang et al., “Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,” in 2017 Symposium on VLSI Technology. IEEE, 2017, pp. T230–T231. 10 X. Huang, C. Liu, Z. Tang, S. Zeng, L. Liu, X. Hou, H. Chen, J. Li, Y.-G. Jiang, D. W. Zhang et al., “High Drive and Low Leakage Current MBC FET with Channel Thickness 1.2 nm/0.6 nm,” in 2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 2020, pp. 12–1. 11, 44 N. Ma and D. Jena, “Charge scattering and mobility in atomically thin semiconductors,” Physical Review X, vol. 4, no. 1, p. 011043, 2014. 20, 40, 42, 46 B. Hu, “Screening-induced surface polar optical phonon scattering in dualgated graphene field effect transistors,” Physica B: Condensed Matter, vol. 461, pp. 118–121, 2015. 20, 21 I.-T. Lin and J.-M. Liu, “Surface polar optical phonon scattering of carriers in graphene on various substrates,” Applied Physics Letters, vol. 103, no. 8, p. 081606, 2013. 21 A. Ghis, E. Constant, and B. Boittiaux, “Ballistic and overshoot electron transport in bulk semiconductors and in submicronic devices,” Journal of applied physics, vol. 54, no. 1, pp. 214–221, 1983. 26 J.-Y. Huang, E.-W. Chang, and Y.-R. Wu, “Optimization of MAPbI 3-Based Perovskite Solar Cell With Textured Surface,” IEEE Journal of Photovoltaics, vol. 9, no. 6, pp. 1686–1692, 2019. 30 T.-Y. Tsai, K. Michalczewski, P. Martyniuk, C.-H. Wu, and Y.-R. Wu, “Application of localization landscape theory and the k• p model for direct modeling of carrier transport in a type II superlattice InAs/InAsSb photoconductor system,” Journal of Applied Physics, vol. 127, no. 3, p. 033104, 2020. 30 S. Smidstrup, T. Markussen, P. Vancraeyveld, J. Wellendorff, J. Schneider, T. Gunst, B. Verstichel, D. Stradi, P. A. Khomyakov, U. G. Vej-Hansen et al., “QuantumATK: An integrated platform of electronic and atomic-scale modelling tools,” J. Phys: Condens. Matter, vol. 32, p. 015901, 2020. 31 M. Hosseini, M. Elahi, M. Pourfath, and D. Esseni, “Strain-Induced Modulation of Electron Mobility in Single-Layer Transition Metal Dichalcogenides MX 2,” IEEE Transactions on Electron Devices, vol. 62, no. 10, pp. 3192–3198, 2015. 32, 35, 65 M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, “Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-k insulator: The role of remote phonon scattering,” Journal of Applied Physics, vol. 90, no. 9, pp. 4587–4608, 2001. 42 L. Zeng, Z. Xin, S. Chen, G. Du, J. Kang, and X. Liu, “Remote phonon and impurity screening effect of substrate and gate dielectric on electron dynamics in single layer MoS2,” Applied Physics Letters, vol. 103, no. 11, p. 113505, 2013. 42 M. Okada, N. Okada, W.-H. Chang, T. Endo, A. Ando, T. Shimizu, T. Kubo, Y. Miyata, and T. Irisawa, “Gas-source CVD growth of atomic layered WS 2 from WF 6 and H 2 S precursors with high grain size uniformity,” Scientific reports, vol. 9, no. 1, pp. 1–10, 2019. 44 Y. Wu, Y.-m. Lin, A. A. Bol, K. A. Jenkins, F. Xia, D. B. Farmer, Y. Zhu, and P. Avouris, “High-frequency, scaled graphene transistors on diamond-like carbon,” Nature, vol. 472, no. 7341, pp. 74–78, 2011. 45 A. Sanne, R. Ghosh, A. Rai, M. N. Yogeesh, S. H. Shin, A. Sharma, K. Jarvis, L. Mathew, R. Rao, D. Akinwande et al., “Radio frequency transistors and circuits based on CVD MoS2,” Nano letters, vol. 15, no. 8, pp. 5039–5045, 2015. 45 J. Robertson and R. M.Wallace, “High-K materials and metal gates for CMOS applications,” Materials Science and Engineering: R: Reports, vol. 88, pp.1–41, 2015. 46 T. Knobloch, Y. Y. Illarionov, F. Ducry, C. Schleich, S. Wachter, T. M¨uller, M. Waltl, M. Lanza, M. I. Vexler, M. Luisier et al., “On the suitability of hBN as an insulator for 2D material-based ultrascaled CMOS devices,” arXiv preprint arXiv:2008.04144, 2020. 46 S.Walia, S. Balendhran, Y.Wang, R. Ab Kadir, A. Sabirin Zoolfakar, P. Atkin, J. Zhen Ou, S. Sriram, K. Kalantar-Zadeh, and M. Bhaskaran, “Characterization of metal contacts for two-dimensional MoS2 nanoflakes,” Applied Physics Letters, vol. 103, no. 23, p. 232105, 2013. 46 T. Yamaguchi, R. Moriya, Y. Inoue, S. Morikawa, S. Masubuchi, K.Watanabe, T. Taniguchi, and T. Machida, “Tunneling transport in a few monolayer-thick WS2/graphene heterojunction,” Applied Physics Letters, vol. 105, no. 22, p. 223109, 2014. 46 T. Ando, N. D. Sathaye, K. V. Murali, and E. A. Cartier, “On the Electron and Hole Tunneling in a HfO2 Gate Stack With Extreme Interfacial-Layer Scaling,” IEEE electron device letters, vol. 32, no. 7, pp. 865–867, 2011. 46 T. Cheiwchanchamnangij andW. R. Lambrecht, “Quasiparticle band structure calculation of monolayer, bilayer, and bulk MoS 2,” Physical Review B, vol. 85, no. 20, p. 205302, 2012. 46 A. Hichri, I. B. Amara, S. Ayari, and S. Jaziri, “Dielectric environment and/or random disorder effects on free, charged and localized excitonic states in monolayer WS2,” Journal of Physics: Condensed Matter, vol. 29, no. 43, p. 435305, 2017. 46 W. Li, J. Zhou, S. Cai, Z. Yu, J. Zhang, N. Fang, T. Li, Y.Wu, T. Chen, X. Xie et al., “Uniform and ultrathin high-k gate dielectrics for two-dimensional electronic devices,” Nature Electronics, vol. 2, no. 12, pp. 563–571, 2019. 53 Y.-C. Yeo, T.-J. King, and C. Hu, “MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations,” IEEE Transactions on Electron Devices, vol. 50, no. 4, pp. 1027–1035, 2003. 53 H. Zhang, B. Shi, L. Xu, J. Yan, W. Zhao, Z. Zhang, Z. Zhang, and J. Lu, “Sub-5 nm Monolayer MoS2 Transistors toward Low-Power Devices,” ACS Applied Electronic Materials, vol. 3, no. 4, pp. 1560–1571, 2021. 55 A. Leonhardt, D. Chiappe, V. V. Afanas’ ev, S. El Kazzi, I. Shlyakhov, T. Conard, A. Franquet, C. Huyghebaert, and S. de Gendt, “Material-Selective Doping of 2D TMDC through Al x O y Encapsulation,” ACS applied materials interfaces, vol. 11, no. 45, pp. 42 697–42 707, 2019. 57 K. Xu, Y.Wang, Y. Zhao, and Y. Chai, “Modulation doping of transition metal dichalcogenide/oxide heterostructures,” Journal of Materials Chemistry C, vol. 5, no. 2, pp. 376–381, 2017. 57 C. J. McClellan, E. Yalon, K. K. Smithe, S. V. Suryavanshi, and E. Pop, “High Current Density in Monolayer MoS2 Doped by AlO x,” ACS nano, vol. 15, no. 1, pp. 1587–1596, 2021. 57, 58 S.-F. Chen and Y.-R. Wu, “Electronic properties of MoS2 nanoribbon with strain using tight-binding method,” physica status solidi (b), vol. 254, no. 2, p. 1600565, 2017. 65 X. Zou, J. Xu, H. Huang, Z. Zhu, H. Wang, B. Li, L. Liao, and G. Fang, “A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2,” Nanotechnology, vol. 29, no. 24, p. 245201, 2018. 65
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/79729-
dc.description.abstract本研究以蒙地卡羅法討論二硫化鉬以及二硫化鎢的傳輸特性,經模擬後得知二硫 化鉬及二硫化鎢的電子遷移率分別為171 cm2/V-s 及83 cm2/V-s。此外,能帶中,K 能谷以及Q 能谷間的能量差是影響材料傳輸特性的重要因素。但若將二維材料周圍以高介電係數材料包覆,遠程聲子散射將會成為最重要降低材料速度的因子。我們將討論完的材料特性帶入二維奈米片電晶體討論元件特性。材料、閘極長度、電極交疊區域、介電層以及電子摻雜將被討論。我們發現相較於二硫化鎢,二硫化鉬會是較好的通道材料。至於介電層,因三氧化二鋁較二氧化鉿有較低的遠程聲子散射,會是較好的介電層材料。電極交疊區域縮短以及摻雜能給電流帶來正面的效應。至於閘極長度的選擇,則要在縮短閘極的好處以及閘極控制力下降間來選擇。在眾多的參數間進行優化後,我們設計出一電晶體,其閘極長度七奈米,電極交疊區域一奈米,介電層為等效氧化層厚度0.8 奈米之氧化鋁以及電子摻雜為4×1013 cm-2。此電晶體在操作電壓0.65伏以及截止電流為1×10-4 μA/μm 下,開路電流可達495 μA/μm,符合國際半導體技術發展藍圖於2022 年對電流之要求。此外,其亦展現出良好的閘極控制能力。zh_TW
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dc.description.tableofcontents"Verification Letter i Acknowledgement ii Chinese Abstract iii English Abstract iv List of Figures ix List of Tables xvi 1 Introduction 1 1.1 Overview of Two-dimensional Materials . . . . . . . . . . . . . . 1 1.2 Introduction and Applications of TMD Materials . . . . . . . . . 2 1.3 Simulation of the Transport Properties . . . . . . . . . . . . . . . 6 1.4 MoS2 and WS2 FET . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 Gate-All-Around Nanosheet Transistor . . . . . . . . . . . . . . . 10 1.6 International Roadmap for Devices and Systems . . . . . . . . . . 12 2 Methodology 15 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Scattering Mechanism and Scattering Rate . . . . . . . . . . . . . 15 2.2.1 Acoustic Phonon Scattering . . . . . . . . . . . . . . . . 17 2.2.2 Optical Phonon: Deformation Potential Scattering . . . . 18 2.2.3 Intervalley Phonon Scattering . . . . . . . . . . . . . . . 19 2.2.4 Remote Phonon Scattering . . . . . . . . . . . . . . . . . 20 2.3 Multi-valley Monte Carlo Method . . . . . . . . . . . . . . . . . 22 2.3.1 Monte Carlo Method . . . . . . . . . . . . . . . . . . . . 22 2.3.2 Multi-valley and non-parabolic band conditions . . . . . . 25 2.3.3 Transient Transport Calculation . . . . . . . . . . . . . . 26 2.4 Monte Carlo, Poisson and Drift-Diffusion Model . . . . . . . . . 27 2.4.1 Poisson and Drift-Diffusion Model . . . . . . . . . . . . 27 2.4.2 Monte Carlo, Poisson and Drift-Diffusion Model . . . . . 28 2.4.3 Two Dimensional Poisson, Drift-Diffusion, and Schrodinger Solver . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 Transport Properties of MoS2 and WS2 31 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 Band structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2.1 Band structure by DFT . . . . . . . . . . . . . . . . . . . 32 3.2.2 Band structure fitting . . . . . . . . . . . . . . . . . . . . 33 3.3 Intrinsic Electrical Transport Properties . . . . . . . . . . . . . . 34 3.4 Extrinsic Transport Properties . . . . . . . . . . . . . . . . . . . 39 3.4.1 Remote Phonone Scattering . . . . . . . . . . . . . . . . 40 4 MoS2 and WS2 Based Transistor 44 4.1 Structures and Simulation Model of 2D Nanosheet Transistors . . 44 4.2 Comparision of Symmetrical and Asymmetrical Gate . . . . . . . 48 4.3 Effect of Dielectric . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.4 Effect of Lun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5 Effect of Doping . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6 Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 Conclusion and Future Work 63 Reference 67 Appendices 85 A Deformation potential constants for MoS2 and WS2 86"
dc.language.isoen
dc.subject二維材料zh_TW
dc.subject二硫化鉬zh_TW
dc.subject二硫化鎢zh_TW
dc.subject蒙地卡羅法zh_TW
dc.subject二維材料奈米片電晶體zh_TW
dc.subject2D nanosheet transistoren
dc.subjectMoS2en
dc.subjectWS2en
dc.subjectMonte Carlo Methoden
dc.subject2D materialen
dc.title二硫化鉬及二硫化鎢傳輸特性及其電晶體之研究zh_TW
dc.titleStudies of Materials and Transport Properties of MoS2 and WS2 Based Transistorsen
dc.date.schoolyear109-2
dc.description.degree碩士
dc.contributor.oralexamcommittee吳肇欣(Hsin-Tsai Liu),張子璿(Chih-Yang Tseng),陳建宏
dc.subject.keyword二維材料,二硫化鉬,二硫化鎢,蒙地卡羅法,二維材料奈米片電晶體,zh_TW
dc.subject.keyword2D material,MoS2,WS2,Monte Carlo Method,2D nanosheet transistor,en
dc.relation.page88
dc.identifier.doi10.6342/NTU202102554
dc.rights.note同意授權(全球公開)
dc.date.accepted2021-08-24
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept光電工程學研究所zh_TW
顯示於系所單位:光電工程學研究所

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