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標題: | 以無電鍍金垂直連接晶片技術之開發 Electroless Au Plating for the Vertical Interconnection of Chips |
作者: | I-An Weng 翁億安 |
指導教授: | 高振宏 |
關鍵字: | 無電鍍,微流道,垂直接合,銅-銅接合, Chip-to-chip interconnection,Copper Pillar Bonding,Electroless Au Plating,Microfluidic Device, |
出版年 : | 2018 |
學位: | 碩士 |
摘要: | 近年來,隨著半導體內電晶體水平線寬的縮小,利用晶片堆疊組裝的三維積體電路直通矽穿孔技術 (3D Integrated Circuits Through Silicon Vias Technology, 3D IC TSV ) 被視為突破傳統封裝限制的方案之一。在3D IC TSV技術中,利用導通孔 (TSV) 與微銲點 (Micro joints) 等技術進行晶片與晶片間的垂直連結,能有效增加晶片的堆疊密度,並且提昇產品速率與降低功率消耗,亦能達到多功能整合等特性。然而,隨者銲點尺度的縮小,微銲點的接合將面臨與傳統不同的挑戰。為取代以往高溫高壓的接合製成,本實驗結合無電鍍金與微流道技術,開發一低溫且無加壓的垂直連接晶片接合技術。
本實驗欲利⽤控制流場的無電鍍金製造全金屬的接點結構。實驗分為兩部分,第一部分為無電鍍金在微流道內的上鍍性質觀察,在此製備圓弧狀與香菇狀兩種不同形貌的銅柱接點,並研究溫度與流速對無電鍍金金屬化反應的影響。研究發現在不同操作溫度與不同流速的情形下,無電鍍金在微流道內均顯示有填孔的特性,其可能原因為無電鍍液中的安定劑過量吸附於於接點表面,使小孔以外的表面不易金屬化。第二部分為利用無電鍍金在微流道內進行接點的接合。藉由上述所發現的無電鍍金填孔特性,並控制接點間的間距至幾微米,無電鍍金成功金屬化銜接上下接點,並且能補償接點錯位造成的影響。研究結果顯示兩種不同表面處理層的接點,包含無電鍍鎳浸金 (ENIG) 與直接浸金 (DIG) 均能以無電鍍金成功接合於微流道內。本研究亦對接合層特徵進行更深入的探討,無電金於ENIG與DIG的接點上呈現不同的上鍍機制,在ENIG接點的接合層中未有任何接合介面,而在DIG接點的接合層中則有明顯的接合介面,然而,在兩種接合層中皆未觀察到任何孔隙與接縫殘留。此外,本研究亦對無電鍍⾦金屬銜接接點進行電性與可靠度量測,並與錫銲接點進行比較。 Bonding of chips using an electroless Au plating by a microfluidic electroless interconnection process (MELI) is proposed. In this approach, aligned copper pillars are served by a controlled electroless plating flow inside a microchannel in an attempt to form all metal interconnections. Several advantages are achieved, including a low process temperature (50 °C for electroless Au plating), a pressure-free environment, and the simple operation. This study is divided into two parts. The first part of the study focuses on the plating characteristics of electroless Au in a microchannel. Dome-shaped and mushroom-shaped copper pillars are utilized and electrolessly Au plated in the microchannel. It is discovered that electroless Au tends to fill small gaps in the microchannel at different plating temperatures with various flow rates, which might due to the adsorption of stabilizers on the plated surface. The second part of this study demonstrates the feasibility of using electroless Au plating to interconnect chips. Based on the discovery of the gap-filling property, by narrowing the gap size between copper pillars, electroless Au could deposit between the gap of pillars and forms an interconnection. Two kinds of surface treated dome-shaped copper pillars, copper pillars with electroless nickel immersion gold (ENIG) and direct immersion gold (DIG), are successfully jointed by electroless Au plating. The results show that void-free bonding joints could be achieved in both samples. In addition, two kinds of samples show different deposition behaviors, resulting in different morphologies. A grain structure without an interface forms in the copper pillars with ENIG joint, whereas an interface structure forms in the copper pillars with DIG joint. It is also demonstrated that electroless Au plating process is capable of compensating the misalignment as that ability of solder. Furthermore, both of the bonding electricity and mechanical properties are comparable to solder-joints. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/79146 |
DOI: | 10.6342/NTU201802059 |
全文授權: | 有償授權 |
電子全文公開日期: | 2023-08-08 |
顯示於系所單位: | 材料科學與工程學系 |
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ntu-107-R05527002-1.pdf 目前未授權公開取用 | 17.29 MB | Adobe PDF |
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