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標題: | 應用於次20奈米非矩形閘極圖形效應FDSOI積體電路之有效電性估測方法 Efficient Electrical Characteristics Estimation Techniques for Sub 20 nm FDSOI Integrated Circuits with Non-Rectangular Gate Patterning Effects |
作者: | Jia-Syun Cai 蔡佳勳 |
指導教授: | 蔡坤諭(Kuen-Yu Tsai) |
關鍵字: | 等效閘極長度,位置相關的權重方法,電腦輔助設計技術,非矩形電晶體,可製造性設計,反相器,六電晶體靜態隨機存取記憶體, Equivalent Gate Length,location-dependent weighting method,Technology Computer Aided Design,non-rectangular transistors,design for manufacturability,inverter,6T-SRAM, |
出版年 : | 2018 |
學位: | 碩士 |
摘要: | 在次波長等級的微影下,印在晶圓上的影像受到圖形失真的影響,變得和當初設計的不同,這些由非理想光學效應所造成的非矩形圖形會嚴重影響電路的特性及效能。一個有效的方法用來準確地評估非矩形電晶體的電性,對於可製造性設計(design for manufacturability,DFM)的電路設計來說是不可或缺的。目前已經有多種建模方法被提出,用來改善非矩形閘極電晶體電性分析的準確性:1. 傳統的等效閘極長度(Equivalent Gate Length,EGL)方法將非矩形電晶體近似成矩形電晶體。2. 一個新的EGL抽取方法使用位置相關的權重因子來改善電流評估的準確性。
在本論文裡,我們基於前述的位置相關的權重方法,並進一步提出三個單一的EGL抽取方法,在電路模擬中將每一個非矩形電晶體用單一的EGL模型來表示。為了模擬非理想光學效應造成的非矩形電晶體並比較不同EGL抽取方法的準確性,我們將著重在TCAD的模擬上。 我們將權重方法及不同的EGL抽取方法應用到次20奈米的FDSOI電路,包括反相器(Inverter)及六電晶體靜態隨機存取記憶體(6T-SRAM),並透過一個後微影模擬流程來預測電路微影後的效能。我們使用一個內部的極紫外光微影(Extreme Ultraviolet Lithography,EUVL)模擬工具來模擬非矩形圖形,電晶體形狀的資料被輸入到TCAD來建立3D的非矩形FDSOI電晶體模型,並藉由TCAD電路模擬來驗證位置相關的權重方法和不同EGL抽取方法的準確性。由於3D TCAD的模擬時間過長,所以我們提出一個使用TCAD的2D EGL電路模擬方法來減少所需的模擬時間。初步的模擬結果指出,權重因子能夠改善電性評估的準確性,特別是在漏電流的分析。通常來說,通道關閉狀態的EGL(Off-state Equivalent Gate Length,EGLoff)加上權重已經夠好了。將來我們也能從TCAD元件抽取出SPICE模型的參數,來做SPICE的模擬。 In subwavelength lithography, the printed patterns on the silicon wafer suffer from geometric distortions and different from the original design. These non-rectangular patterns which caused by non-ideal optical effects can affect electrical characteristics and performances of circuits seriously. An efficient approach to estimate the electrical characteristics of non-rectangular transistors accurately is indispensable for the design for manufacturability (DFM) circuit design. There have been many modeling approaches that are proposed for improving the accuracy of electrical characteristics analysis of non-rectangular gate transistors: 1) the conventional equivalent gate length (EGL) modeling method approximates a non-rectangular transistor with rectangular transistors. 2) A new EGL extraction method uses the location-dependent weighting factors to improve the estimation accuracy of electric current. In this thesis, we are based on the location-dependent weighting method as mentioned above and further propose three single EGL extraction methods for representing each non-rectangular gate transistor with a single EGL model in circuit simulation. In order to simulate the non-rectangular transistors caused by non-ideal optical effects and compare the accuracy of different EGL extraction methods, we will focus on the TCAD simulation. The weighting method and different EGL extraction methods are applied to sub-20nm FDSOI circuits including inverter and 6T-SRAM and the performances of post-lithography circuits are predicted through a post-lithography simulation flow. An in-house Extreme Ultraviolet Lithography (EUVL) simulation tool is utilized for non-rectangular pattern simulation. Shape information of the transistors is imported to TCAD to construct 3D non-rectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and different EGL extraction methods are verified by TCAD circuit simulations. Because 3D TCAD simulation take too much simulation time, we propose a 2D EGL circuit simulation method in TCAD to reduce the simulation time required. Preliminary simulation results indicate that the weighting factors can improve the accuracy of electrical characteristics estimation, especially in the leakage current analysis. The off-state EGL (EGLoff) with weightings is usually good enough. We may extract SPICE model parameters from the TCAD device to run the SPICE simulations in the future. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/79008 |
DOI: | 10.6342/NTU201803345 |
全文授權: | 有償授權 |
電子全文公開日期: | 2023-08-21 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-107-R04943152-1.pdf 目前未授權公開取用 | 13.91 MB | Adobe PDF |
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