利用原子層沉積技術於金屬閘極與高介電係數介電層堆疊之特性優化及鐵電二氧化鋯薄膜研究

Abstract

本論文的主題為研究開發先進的原子層沉積(atomic layer deposition, ALD)技術，並進一步應用於高效能金屬閘極(metal gate)、高介電係數閘極介電層(high-k gate dielectrics)、以及鐵電(ferroelectric)薄膜與元件。 為了開發適用於互補型金屬氧化物半導體(complementary metal-oxide-semiconductor, CMOS)元件的薄膜金屬閘極材料，並達到降低金屬氧化物半導體場效應電晶體(metal-oxide-semiconductor field-effect-transistor, MOSFET)閾值電壓的效果，本論文首先研究使用原子層摻雜(atomic layer doping)技術來調控金屬閘極之功函數。在此研究中，我們製備摻雜了氮化鋁(AlN)的氮化鈦(TiN)混層金屬(Ti1-xAlxNy)，以調整Ti1-xAlxNy金屬閘極的功函數。所採用之原位(in-situ)原子層片層摻雜(lamellar doping)技術，可以精確地控制Ti1-xAlxNy薄膜中氮化鋁的摻雜濃度。隨著定義上(nominal)之AlN片層摻雜率(DPAlN)從0%增加到50%時，Ti1-xAlxNy金屬閘極的功函數從4.49 eV下降到4.19 eV(當DPAlN為6.25%時)；而後在DPAlN為50%時，其功函數上升至4.59 eV。在Ti1-xAlxNy金屬閘極中所發現的低功函數(4.19 eV)適用於n-MOSFET元件，為金屬閘極的低功函數調控提供了一條可行的途徑。 為了提高二氧化鋯(ZrO2)高介電係數閘極介電層的電性表現，我們引入原位、逐層的原子層氫氣電漿轟擊(atomic layer hydrogen bombardment, ALHB)技術到傳統的原子層沉積迴圈(ALD cycles)當中。由於氫氣電漿中所攜帶的能量可傳遞至薄膜表面，ALHB技術有助於薄膜中每層原子的遷移，並紓減反應前驅物(precursor)堆疊時的立體阻障。從X光反射率(X-ray reflectivity, XRR)和X光光電子能譜(X-ray photoelectron spectroscopy)的分析結果中，佐證了ALHB技術導致薄膜的緻密化，並抑制了二氧化鋯薄膜中氧空缺的含量。除此之外，在金屬-氧化物-半導體(metal-oxide-semiconductor, MOS)和金屬-絕緣體-金屬(metal-insulator-metal, MIM)電容元件中，有使用ALHB技術處理過後的元件，其閘極漏電流密度(gate leakage current density, Jg)降低了大約90%，同時在MOS與MIM電容元件中，分別擁有電容等效厚度(capacitance equivalent thicknesses, CET)約1.3 nm和約0.6 nm的優秀表現。結果表明，在提升奈米薄膜電性表現上ALHB為十分有前景的技術，並有助於感測器、太陽能電池、記憶體和奈米電子元件等先進元件的改良與突破。 在第三部分的研究中，我們展示了具鐵電特性的6.5 nm純二氧化鋯(ZrO2)薄膜，且其擁有約50 µCcm-2的巨大殘餘極化量(remanent polarization, Pr)及約7–9 pm/V的等效壓電係數(effective piezoelectric coefficient, d33)。該二氧化鋯薄膜是利用電漿增強型原子層沉積(plasma-enhanced ALD)技術在製程溫度300 °C下，將其薄膜沉積於具立方晶系(cubic)之(111)晶面擇優取向之白金電極上，再搭配400 °C之退火製程，進而在二氧化鋯薄膜中，產生正交晶系(orthorhombic)之(111)晶面平行於基材表面的擇優結晶方向。該約50 µCcm-2的巨大殘餘極化量，為目前所有沉積於白金電極上之鈣鈦礦和螢石系列的奈米鐵電薄膜(厚度小於120 nm)中，所報導過最大的數值。此外，製備該二氧化鋯薄膜之300–400 °C的加工溫度，是迄今為止在白金電極上，具殘餘極化量大於50 µCcm-2之奈米級鐵電材料的製備中，所報導的最低溫度。利用鐵電正上負下(positive-up negative down, PUND)測量方法，搭配數十秒的延遲時間的量測參數，以排除因極化釋放不完全可能造成之高估，我們確認了該來自擇優結晶方向所帶來的巨大殘餘極化量的正確性。二氧化鋯薄膜之等效壓電係數的量測，是利用搭配了干涉式位移感測器的壓電力顯微鏡(piezoresponse force microscopy, PFM)，以期最小化頻率相關的誤判和懸臂梁做動所造成的影響。此具有特別質地(texture)和巨大殘餘極化量之極薄二氧化鋯薄膜，對於先進奈米電子元件中的尺寸微縮和製程整合，具有極大的優勢。 最後，本論文進一步研究金屬-鐵電-半導體(metal-ferroelectric-semiconductor, MFS)電容及鐵電電晶體(ferroelectric FET, FeFET)元件，並使用二氧化鉿(HfO2)晶種層在400 °C的低熱預算(thermal budget)下，實現了奈米級二氧化鋯薄膜之鐵電特性的增強。來自二氧化鉿的晶種效應，增強了小於6 nm的二氧化鋯/二氧化鉿雙層結構中，正交晶相之結晶度及其殘餘極化量；並由其電容元件中電容等效厚度之下降與漏電流的抑制可知，二氧化鉿晶種層有效優化了薄膜的介電特性。在以二氧化鋯/二氧化鉿雙層結構作為閘極堆疊之鐵電電晶體的表現中，呈現了約1.2 V之大的記憶體區間(memory window)以及小於60 mV/decade之陡的次臨界擺幅(subthreshold swing)。在與氧化鋯鉿(Hf0.5Zr0.5O2)的比較中，二氧化鋯/二氧化鉿雙層結構所具有的突出鐵電與介電特性，展現了其在鐵電邏輯與記憶元件與矽基板整合之優秀潛力。

In this thesis, advanced atomic layer deposition (ALD) techniques were investigated to improve the performance of the metal gate, high-k gate dielectrics, and ferroelectric materials and devices. In the first part of this thesis, the in-situ atomic layer doping technique was studied in order to obtain an appropriate metal gate material for a low threshold voltage in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in complementary metal-oxide-semiconductor (CMOS) applications. Atomic AlN layers were introduced into TiN to tailor the work function of the Ti1-xAlxNy metal gate electrode. Using the in-situ atomic layer lamellar doping technique, the AlN doping concentration in the thin Ti1-xAlxNy layer can be precisely controlled. With the increase of the nominal AlN lamellar doping percentage (DPAlN) from 0% to 50%, the work function of the Ti1-xAlxNy metal gate decreases from 4.49 eV and reaches a minimum of 4.19 eV as the DPAlN equals to 6.25%, and then increases to 4.59 eV with the DPAlN of 50%. The low work function (4.19 eV) of the Ti1-xAlxNy metal gate is appropriate for n-MOSFETs, which demonstrates a feasible way to achieve the low work function engineering of metal gate. In the second part of this thesis, a layer-by-layer, in-situ H2 plasma treatment in each cycle of atomic layer deposition, referred to as “atomic layer hydrogen bombardment” (ALHB), was developed to improve electrical properties of ZrO2 high-k gate dielectrics. The H2 plasma bombardment facilitates the adatom migration due to energy delivery to each as-deposited monolayer from the H2 plasma. In addition, the H2 plasma treatment contributes to the removal of precursor ligands for the release of steric hindrance. Hence the ALHB treatment leads to the film densification and the suppression of oxygen vacancies of ZrO2, as evidenced by X-ray reflectivity and X-ray photoelectron spectroscopy characterizations. As a result, ~90% decrease of the gate leakage current is achieved in the ZrO2 high-k gate dielectrics with capacitance equivalent thicknesses (CET) of ~1.3 nm and ~0.6 nm in metal-insulator-semiconductor and metal-insulator-metal capacitors, respectively. The results manifest that the ALHB treatment is a promising technique to enhance dielectric and electrical characteristics of nanoscale thin films, for further progress of advanced devices such as sensors, solar cells, memories, and nanoelectronics. In the third part of this thesis, a ~6.5 nm pure ZrO2 thin film with a giant ferroelectric remanent polarization (Pr) of ~50 μCcm-2 and an effective piezoelectric coefficient (d33) of 7–9 pm/V is reported. The film was prepared on a (111)-oriented Pt electrode using plasma-enhanced atomic layer deposition at 300 C followed by annealing at 400 C. The ZrO2 layer exhibited a preferred orientation of the orthorhombic (111) planes in the in-plane direction. The Pr of ~50 μCcm-2 is the largest reported to date for both perovskite and fluorite nanoscale ferroelectric thin films (< 120 nm) on a Pt electrode. Furthermore, the processing temperature of 300-400 C is the lowest reported to date to produce a Pr larger than 50 μCcm-2 in nanoscale ferroelectrics on a Pt electrode. The giant Pr, ascribed to the preferred crystal orientation, was confirmed by the positive-up negative-down (PUND) polarization measurement with a long delay time to allow the relaxation of polarization. The effective d33 was obtained using piezoresponse force microscopy with an interferometric displacement sensor to minimize frequency-dependent artifacts and the effects of cantilever dynamics. The low-temperature preparation of the textured ZrO2 ultrathin film with a giant Pr is extremely advantageous for device scaling and process integration in advanced nanoelectronics. Finally, enhanced ferroelectric properties of nanoscale ZrO2 thin films by an HfO2 seed layer is demonstrated in metal-ferroelectric-semiconductor capacitors and transistors prepared with a low thermal budget of 400 °C. The seeding effect of the HfO2 layer leads to the enhancement of the orthorhombic phase crystallization and the increase of the remanent polarization (2Pr) of a sub-6 nm ZrO2/HfO2 bilayer structure. The HfO2 seed layer also contributes to the improved dielectric properties in terms of the decrease of the capacitance equivalent thickness and the leakage current. The ferroelectric field-effect transistor with the ZrO2/HfO2 bilayer gate stack is also demonstrated with a large memory window of ~1.2 V and a steep subthreshold swing below 60 mV/decade. As compared with the Hf0.5Zr0.5O2 thin film, the superior ferroelectric and dielectric properties of the ZrO2/HfO2 bilayer structure show great potentials for the ferroelectric logic and memory devices fabricated on Si substrates.