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標題: | 常關式氮化鎵大面積高電子遷移率電晶體之製作與分析 Fabrication and Analysis of Large Area Enhancement mode GaN High Electron Mobility Transistors |
作者: | Yu-Li Ho 何竽曆 |
指導教授: | 吳肇欣(Chao-Hsin Wu) |
共同指導教授: | 黃定洧(Ding-Wei Huang) |
關鍵字: | p 型氮化鎵/氮化鋁鎵/氮化鎵異質接面結構,高電子遷移率電晶體,大電流元件,寄生電容量測,drain lag 與gate lag 量測, p-GaN/AlGaN/GaN heterostructure,HEMTs,large current devices,parasitic capacitance measurement,drain lag and gate lag measurement, |
出版年 : | 2020 |
學位: | 碩士 |
摘要: | 在多年前傳統的MOS功率元件已發展到了瓶頸,在切換速率及耐溫耐壓方面遠不及寬能隙半導體,氮化鋁鎵/氮化鎵憑藉著異質結構形成的電子氣通道,達到高電子遷移率特性,在氮化鋁鎵層上方加一層p型摻雜的氮化鎵層,可以將通道區能帶提高至費米能接以上,使電晶體由空乏型轉變為增強型,提升在電路應用上的安全性。p型摻雜層閘極結構為目前常見的增強型氮化鎵電晶體,但是此結構仍然存在一些問題值得被探討,如閘極區外的p型摻雜層蝕刻深度及蝕刻平整度的掌握、p型摻雜層厚度對電晶體特性的影響、閘極區p-i-n結構形成的漏流等等。本論文我們採用跨接式閘極結構來提升元件輸出功率,並且進行不同p型摻雜層厚度、元件尺寸的電性比較。 此碩論可分為四個部分,第一部分簡單講述氮化鎵高電子遷移率電晶體相對於傳統MOS功率元件所擁有的優勢,及氮化鋁鎵/氮化镓的基本材料特性,第二部分內容為p型摻雜層蝕刻測試的過程,利用雷射端點偵測系統提高蝕刻深度的準確性,採用傳輸線理論模型量測並萃取得接觸電阻,並且比較不同蝕刻參數下的蝕刻表面粗糙度及電性。第三部分為元件直流特性數據分析,為了得到合適的大面積電晶體尺寸,此研究做了閘極寬度及閘極指數提升時在電性上所帶來的效應,同時比較了50奈米及70奈米p型摻雜層兩版磊晶結構在直流電性上的差異。最後一部分可分為兩個重點,首先為了探討元件的切換特性,我們進行了Ciss、Coss、Crss寄生電容量測,並對不同p型摻雜層厚度及不同尺寸元件進行比較,接著我們量測了drain lag、gate lag特性,並在相同偏壓下進行歸一化後的導通電阻比較,最後將脈衝量測結果與直流特性作對照。 在50奈米及70奈米p型摻雜層磊晶結構上做出的60毫米大電流元件飽和輸出電流密度分別為43 mA/mm、31 mA/mm,臨界電壓分別為0.4 V、2.8 V。在相似尺寸元件比較上,閘極寬度60微米40指元件輸出電流密度比閘極寬度2500微米單指元件還大9倍。同樣為60毫米大電流元件,50奈米及70奈米p型摻雜層磊晶結構上所量到的Ciss、Coss、Crss 分別為112 pF、7.25 pF、6.34 pF及43.8 pF、8.98 pF、5.62 pF。同樣為閘極寬度3.6毫米元件,於drain lag 量測的(VGSQ,VDSQ = 0,40)靜態偏壓點,50奈米及70奈米p型摻雜層磊晶結構上量到的Ron上升率分別為1.63及3.26倍,於gate lag量測的(VGSQ,VDSQ = -10,0)靜態偏壓點,50奈米及70奈米p型摻雜層磊晶結構上量到的Ron上升率分別為1.13及1.05倍 Many years ago, traditional MOS power devices have reached a bottleneck in which they are far inferior to wide-bandgap semiconductors in terms of switching rate and temperature and voltage tolerance. AlGaN/GaN relies on the electron gas channel formed by the heterostructure to achieve high electrons mobility characteristics. Adding a p-type doped gallium nitride layer above the aluminum gallium nitride layer can increase the energy band of the channel region above the Fermi level, so that the transistor is transformed from depletion type to the enhancement type, promoting safety in circuit applications. The p-GaN gate structure is presently a common feature of enhancement mode gallium nitride transistors, but there are still some problems with this structure that deserve to be discussed, such as the control of the etching depth and the etching uniformity of the p-GaN outside the gate region, the influence of the thickness of the p-GaN on the characteristics of the transistor, the leakage current formed by the p-i-n structure of the gate region, and etc. In this thesis, we used an interdigitated finger structure to increase the output power of the p-GaN HEMT device, and compared the performance of devices with different p-GaN thicknesses, geometry. The thesis can be divided into four parts. The first part briefly describes the advantages of gallium nitride high electron mobility transistors over traditional MOS power devices, and the basic material characteristics of AlGaN/GaN. The second part discusses the p-GaN etching test. In this process, a laser endpoint detection system is used to improve the accuracy of the etching depth, and the transmission line method is used to measure rhe contact resistance. We compared the roughness and electrical properties of the etched surface under different etching parameters. The third part is the data analysis of the device DC characteristics. In order to obtain the appropriate high-current transistor design, we analyzed the electrical effect of increasing the gate width and number of gate fingers, and compared the output current performance of a 50 nm versus a 70 nm thick p-GaN layer. The last part can be divided into two important points. First, in order to explore the switching characteristics of the device, we conducted parasitic capacitance measurements (input capacitance Ciss, output capacitance Coss, and reverse transfer capacitance Crss) comparing the different p-GaN thicknesses at different geometry of the device. Then we measured the drain lag and gate lag characteristics, and the normalized on-resistance of the devices is compared under the same bias voltage. Finally, the pulse measurement results are compared with the DC characteristics. The results showed the saturation output current densities of the large area devices using 50 nm and 70 nm p-GaN were 43 mA/mm and 31 mA/mm, and the threshold voltages Vth were 0.4 V and 2.8 V, respectively. The output current density of a 40-finger device with a gate width of 60 µm is 9 times greater than that of a single-finger device with a gate width of 2500 µm. Using a gate width of 60 mm, the Ciss, Coss, and Crss measured on the 50 nm and 70 nm p-GaN device are 112 pF, 7.25 pF, and 6.34 pF, respectively, and 43.8 pF, 8.98 pF, and 5.62 pF, respectively, for the 70 nm p-GaN device. With a gate width of 3.6 mm, the on-resistance rise rates measured by drain lag (VGSQ,VDSQ = 0, 40 V) on the 50 nm and 70 nm p-GaN devices were 1.63 and 3.26, respectively, and the on-resistance rise rates measured by gate lag (VGSQ,VDSQ = -10, 0 V) were 1.13 and 1.05, respectively. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78595 |
DOI: | 10.6342/NTU202004401 |
全文授權: | 有償授權 |
電子全文公開日期: | 2023-12-03 |
顯示於系所單位: | 光電工程學研究所 |
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