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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳肇欣(Chao-Hsin Wu) | |
dc.contributor.author | Yu-Li Ho | en |
dc.contributor.author | 何竽曆 | zh_TW |
dc.date.accessioned | 2021-07-11T15:06:13Z | - |
dc.date.available | 2023-12-03 | |
dc.date.copyright | 2021-01-05 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-12-09 | |
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Lidow, 'Can gallium nitride replace silicon?,' Power Electronics Europe, no. 2, pp. 30-33, 2010. [7] F. Roccaforte, G. Greco, P. Fiorenza, and F. Iucolano, 'An overview of normally-off GaN-based high electron mobility transistors,' Materials, vol. 12, no. 10, p. 1599, 2019. [8] N. Kaminski and O. Hilt, 'SiC and GaN devices–wide bandgap is not all the same,' IET Circuits, Devices Systems, vol. 8, no. 3, pp. 227-236, 2014. [9] T. Hirose, M. Imai, and K. Watanabe, 'GaN HEMT Technology for Environmentally Friendly Power Electronics,' Fujitsu Sci. Tech. J, vol. 53, no. 6, pp. 74-80, 2017. [10] E. Gurpinar and A. Castellazzi, 'Single-phase T-type inverter performance benchmark using Si IGBTs, SiC MOSFETs, and GaN HEMTs,' IEEE Transactions on Power Electronics, vol. 31, no. 10, pp. 7148-7160, 2015. [11] C.-T. Ma and Z.-H. Gu, 'Review of GaN HEMT applications in power converters over 500 W,' Electronics, vol. 8, no. 12, p. 1401, 2019. [12] H. Li, C. Yao, L. Fu, X. Zhang, and J. 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Hsieh et al., 'Gate recessed quasi-normally OFF Al2O3/AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using PEALD AlN interfacial passivation layer,' IEEE Electron Device Letters, vol. 35, no. 7, pp. 732-734, 2014. [17] Y. Cai, Y. Zhou, K. J. Chen, and K. M. Lau, 'High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment,' IEEE Electron Device Letters, vol. 26, no. 7, pp. 435-437, 2005. [18] O. Hilt, A. Knauer, F. Brunner, E. Bahat-Treidel, and J. Würfl, 'Normally-off AlGaN/GaN HFET with p-type Ga Gate and AlGaN buffer,' in 2010 22nd International Symposium on Power Semiconductor Devices IC's (ISPSD), 2010: IEEE, pp. 347-350. [19] Y. Xu, S. Cristoloveanu, M. Bawedin, K.-S. Im, and J.-H. Lee, 'Performance improvement and sub-60 mV/decade swing in AlGaN/GaN FinFETs by simultaneous activation of 2DEG and sidewall MOS channels,' IEEE Transactions on Electron Devices, vol. 65, no. 3, pp. 915-920, 2018. [20] L.-Y. Shu et al., “Enhancement-mode GaN-based High-Electron mobility transistor on the Si substrate with a p-type GaN cap layer”, IEEE Transaction on Electron Devices, vol. 61, no. 2, pp. 460-465, 2014 [21] C. Zeng et al., 'Investigations of the gate instability characteristics in Schottky/ohmic type p-GaN gate normally-off AlGaN/GaN HEMTs,' Applied Physics Express, vol. 12, no. 12, p. 121005, 2019. [22] N. Posthuma et al., 'Impact of Mg out-diffusion and activation on the p-GaN gate HEMT device performance,' in 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2016: IEEE, pp. 95-98. [23] H.-C. Chiu et al., 'High uniformity normally-OFF p-GaN gate HEMT using self-terminated digital etching technique,' IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 4820-4825, 2018. [24] M. J. Uren, M. Caesar, S. Karboyan, P. Moens, P. Vanmeerbeek, and M. Kuball, 'Electric field reduction in C-doped AlGaN/GaN on Si high electron mobility transistors,' IEEE Electron Device Letters, vol. 36, no. 8, pp. 826-828, 2015. [25] N. M. Shrestha, Y. Y. Wang, Y. Li, and E. Chang, Effect of AIN Spacer Layer on AlGaN/GaN HEMTs. na, 2013. [26] X. Li et al., 'Implementation of slow and smooth etching of GaN by inductively coupled plasma,' Journal of Semiconductors, vol. 39, no. 11, p. 113002, 2018. [27] L. Wang, C. Tan, H. Luo, S. Wang, H. Ye, and X. Chen, 'Paper Title The Breakdown Voltage of AlGaN/GaN HEMT is Restricted to The Structure Parameters of The Device: A Study Based on TCAD,' in 2018 19th International Conference on Electronic Packaging Technology (ICEPT), 2018: IEEE, pp. 961-964. Z [28] X. Zhang, L. Wei, L. Wang, J. Liu, and J. Xu, 'Gate length related transfer characteristics of GaN-based high electron mobility transistors,' Applied Physics Letters, vol. 102, no. 11, p. 113501, 2013. [29] J. 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Ogura, 'Influence of surface defect charge at AlGaN-GaN-HEMT upon Schottky gate leakage current and breakdown voltage,' IEEE Transactions on Electron Devices, vol. 52, no. 2, pp. 159-164, 2005. [35] A. Tajalli et al., 'Impact of sidewall etching on the dynamic performance of GaN-on-Si E-mode transistors,' Microelectronics Reliability, vol. 88, pp. 572-576, 2018. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78595 | - |
dc.description.abstract | 在多年前傳統的MOS功率元件已發展到了瓶頸,在切換速率及耐溫耐壓方面遠不及寬能隙半導體,氮化鋁鎵/氮化鎵憑藉著異質結構形成的電子氣通道,達到高電子遷移率特性,在氮化鋁鎵層上方加一層p型摻雜的氮化鎵層,可以將通道區能帶提高至費米能接以上,使電晶體由空乏型轉變為增強型,提升在電路應用上的安全性。p型摻雜層閘極結構為目前常見的增強型氮化鎵電晶體,但是此結構仍然存在一些問題值得被探討,如閘極區外的p型摻雜層蝕刻深度及蝕刻平整度的掌握、p型摻雜層厚度對電晶體特性的影響、閘極區p-i-n結構形成的漏流等等。本論文我們採用跨接式閘極結構來提升元件輸出功率,並且進行不同p型摻雜層厚度、元件尺寸的電性比較。 此碩論可分為四個部分,第一部分簡單講述氮化鎵高電子遷移率電晶體相對於傳統MOS功率元件所擁有的優勢,及氮化鋁鎵/氮化镓的基本材料特性,第二部分內容為p型摻雜層蝕刻測試的過程,利用雷射端點偵測系統提高蝕刻深度的準確性,採用傳輸線理論模型量測並萃取得接觸電阻,並且比較不同蝕刻參數下的蝕刻表面粗糙度及電性。第三部分為元件直流特性數據分析,為了得到合適的大面積電晶體尺寸,此研究做了閘極寬度及閘極指數提升時在電性上所帶來的效應,同時比較了50奈米及70奈米p型摻雜層兩版磊晶結構在直流電性上的差異。最後一部分可分為兩個重點,首先為了探討元件的切換特性,我們進行了Ciss、Coss、Crss寄生電容量測,並對不同p型摻雜層厚度及不同尺寸元件進行比較,接著我們量測了drain lag、gate lag特性,並在相同偏壓下進行歸一化後的導通電阻比較,最後將脈衝量測結果與直流特性作對照。 在50奈米及70奈米p型摻雜層磊晶結構上做出的60毫米大電流元件飽和輸出電流密度分別為43 mA/mm、31 mA/mm,臨界電壓分別為0.4 V、2.8 V。在相似尺寸元件比較上,閘極寬度60微米40指元件輸出電流密度比閘極寬度2500微米單指元件還大9倍。同樣為60毫米大電流元件,50奈米及70奈米p型摻雜層磊晶結構上所量到的Ciss、Coss、Crss 分別為112 pF、7.25 pF、6.34 pF及43.8 pF、8.98 pF、5.62 pF。同樣為閘極寬度3.6毫米元件,於drain lag 量測的(VGSQ,VDSQ = 0,40)靜態偏壓點,50奈米及70奈米p型摻雜層磊晶結構上量到的Ron上升率分別為1.63及3.26倍,於gate lag量測的(VGSQ,VDSQ = -10,0)靜態偏壓點,50奈米及70奈米p型摻雜層磊晶結構上量到的Ron上升率分別為1.13及1.05倍 | zh_TW |
dc.description.abstract | Many years ago, traditional MOS power devices have reached a bottleneck in which they are far inferior to wide-bandgap semiconductors in terms of switching rate and temperature and voltage tolerance. AlGaN/GaN relies on the electron gas channel formed by the heterostructure to achieve high electrons mobility characteristics. Adding a p-type doped gallium nitride layer above the aluminum gallium nitride layer can increase the energy band of the channel region above the Fermi level, so that the transistor is transformed from depletion type to the enhancement type, promoting safety in circuit applications. The p-GaN gate structure is presently a common feature of enhancement mode gallium nitride transistors, but there are still some problems with this structure that deserve to be discussed, such as the control of the etching depth and the etching uniformity of the p-GaN outside the gate region, the influence of the thickness of the p-GaN on the characteristics of the transistor, the leakage current formed by the p-i-n structure of the gate region, and etc. In this thesis, we used an interdigitated finger structure to increase the output power of the p-GaN HEMT device, and compared the performance of devices with different p-GaN thicknesses, geometry. The thesis can be divided into four parts. The first part briefly describes the advantages of gallium nitride high electron mobility transistors over traditional MOS power devices, and the basic material characteristics of AlGaN/GaN. The second part discusses the p-GaN etching test. In this process, a laser endpoint detection system is used to improve the accuracy of the etching depth, and the transmission line method is used to measure rhe contact resistance. We compared the roughness and electrical properties of the etched surface under different etching parameters. The third part is the data analysis of the device DC characteristics. In order to obtain the appropriate high-current transistor design, we analyzed the electrical effect of increasing the gate width and number of gate fingers, and compared the output current performance of a 50 nm versus a 70 nm thick p-GaN layer. The last part can be divided into two important points. First, in order to explore the switching characteristics of the device, we conducted parasitic capacitance measurements (input capacitance Ciss, output capacitance Coss, and reverse transfer capacitance Crss) comparing the different p-GaN thicknesses at different geometry of the device. Then we measured the drain lag and gate lag characteristics, and the normalized on-resistance of the devices is compared under the same bias voltage. Finally, the pulse measurement results are compared with the DC characteristics. The results showed the saturation output current densities of the large area devices using 50 nm and 70 nm p-GaN were 43 mA/mm and 31 mA/mm, and the threshold voltages Vth were 0.4 V and 2.8 V, respectively. The output current density of a 40-finger device with a gate width of 60 µm is 9 times greater than that of a single-finger device with a gate width of 2500 µm. Using a gate width of 60 mm, the Ciss, Coss, and Crss measured on the 50 nm and 70 nm p-GaN device are 112 pF, 7.25 pF, and 6.34 pF, respectively, and 43.8 pF, 8.98 pF, and 5.62 pF, respectively, for the 70 nm p-GaN device. With a gate width of 3.6 mm, the on-resistance rise rates measured by drain lag (VGSQ,VDSQ = 0, 40 V) on the 50 nm and 70 nm p-GaN devices were 1.63 and 3.26, respectively, and the on-resistance rise rates measured by gate lag (VGSQ,VDSQ = -10, 0 V) were 1.13 and 1.05, respectively. | en |
dc.description.provenance | Made available in DSpace on 2021-07-11T15:06:13Z (GMT). No. of bitstreams: 1 U0001-0712202017071600.pdf: 13303916 bytes, checksum: 0d2362154d276cf3b49101e411f4437b (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 致謝 i 中文摘要 iii ABSTRACT v CONTENTS vii LIST OF FIGURES ix LIST OF TABLES xv Chapter 1 緒論 1 1.1 背景介紹 1 1.2 氮化鎵材料特性介紹 5 1.3 研究動機與論文概述 8 Chapter 2 p型摻雜閘極高電子遷移率電晶體開發與蝕刻製程測試 9 2.1 p型摻雜閘極高電子遷移率電晶體文獻回顧 9 2.2 磊晶結構設計 14 2.3 p型摻雜層蝕刻測試 15 2.3.1 氮化鎵蝕刻原理 15 2.3.2 端點偵測系統 End-point Detector 17 2.3.3 p型摻雜層蝕刻測試 19 2.4 傳輸線模型TLM電性測試 23 2.4.1 傳輸線模型理論 Transmission Line Model 23 2.4.2 傳輸線模型(TLM)量測結果 25 2.4.3 不同蝕刻參數結果比較 30 Chapter 3 p型摻雜閘極大電流高電子遷移率電晶體之製作與分析 33 3.1 實驗介紹與光罩設計 33 3.2 p型摻雜閘極大電流電晶體之製作流程 36 3.3 p型摻雜閘極電晶體直流特性分析 42 3.3.1 50奈米p型摻雜層元件直流特性分析 42 3.3.2 70奈米p型摻雜層元件直流特性分析 51 Chapter 4 p-GaN大電流高電子遷移率電晶體寄生電容、脈衝電性量測 59 4.1 寄生電容量測 59 4.1.1 寄生電容 59 4.1.2 寄生電容量測架設 62 4.1.3 寄生電容量測結果與分析 66 4.2 脈衝電性量測 71 4.2.1 表面缺陷與基板缺陷 71 4.2.2 脈衝電性量測與分析 73 Chapter 5 結論與未來展望 78 REFERENCE 80 | |
dc.language.iso | zh-TW | |
dc.title | 常關式氮化鎵大面積高電子遷移率電晶體之製作與分析 | zh_TW |
dc.title | Fabrication and Analysis of Large Area Enhancement mode GaN High Electron Mobility Transistors | en |
dc.type | Thesis | |
dc.date.schoolyear | 109-1 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 黃定洧(Ding-Wei Huang) | |
dc.contributor.oralexamcommittee | 吳添立(Tian-Li Wu),鄒安傑(An-Jye Tzou) | |
dc.subject.keyword | p 型氮化鎵/氮化鋁鎵/氮化鎵異質接面結構,高電子遷移率電晶體,大電流元件,寄生電容量測,drain lag 與gate lag 量測, | zh_TW |
dc.subject.keyword | p-GaN/AlGaN/GaN heterostructure,HEMTs,large current devices,parasitic capacitance measurement,drain lag and gate lag measurement, | en |
dc.relation.page | 85 | |
dc.identifier.doi | 10.6342/NTU202004401 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2020-12-10 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
dc.date.embargo-lift | 2023-12-03 | - |
顯示於系所單位: | 光電工程學研究所 |
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