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標題: | 多通道奈米線氧化銦鎵鋅薄膜電晶體之研究 Multi-channel nanowire InGaZnO Thin-Film Transistors |
作者: | Jiun-Yu Chen 陳俊瑜 |
指導教授: | 陳奕君(I-Chun Cheng) |
關鍵字: | 非晶氧化銦鎵鋅,n型氧化物半導體,薄膜電晶體,電子束微影,奈米線電晶體,多通道結構,偏壓穩定性, amorphous indium-gallium-zinc-oxide (a-IGZO),n-type oxide semiconductors,electron-beam lithography (EBL),nanowire transistors,multi-channel structures,gate bias stress stability, |
出版年 : | 2019 |
學位: | 碩士 |
摘要: | 本研究致力於開發奈米線單通道與多通道氧化銦鎵鋅薄膜電晶體,探討通道寬度及結構組成對元件電特性的影響。研究中使用電子束微影技術來達到次微米級通道寬度。通道寬度為0.3 µm之薄膜電晶體,其電子遷移率約為12 cm2/Vs,相較於寬度為40 µm之元件的電子遷移率8 cm2/Vs,提升了~50%,其成因可能是通道缺陷數量的減少。奈米線薄膜電晶體其臨界電壓隨著通道寬度的縮小,呈現上升的趨勢,造成此現象的原因可能來自於通道表面電荷空乏較為嚴重。
本研究另一個重點在於多通道奈米線結構設計與其特性表現探討。由0.3 µm寬奈米線所組成之多通道結構,相較其等效單通道結構,電子遷移率提升約75%至80%。由四條微米與次微米級寬度組成之多通道結構薄膜電晶體,其電特性表現,相較於等效單通道結構,除因次通道由奈米線組成而造成臨界電壓略為上升以外,並沒有顯著的差異。四條多通道結構薄膜電晶體,電子遷移率未被明顯提升的原因,為其主通道寬度停留在微米等級。固定通道寬度、改變通道間距時,寬間距的元件偏壓穩定性表現較窄間距佳,此現象為具有較大通道間距、可以協助元件散熱之多通道結構設計所貢獻。在偏壓穩定性測試下,主通道寬度較寬、間距較窄;次通道寬度較窄、間距較寬的多通道結構,在施加 VG = 10 V偏壓 10000 秒後,其臨界電壓偏移僅0.43 V,元件特徵捕獲時間約為3.03×1010秒、β值約為0.20;相較等效單通道結構臨界電壓偏移量0.81 V,特徵捕獲時間約為7.98×108秒、β值約為0.20,其穩定性大幅提升,臨界電壓偏移量減少約53%,特徵捕獲時間約得以提升38倍,多通道結構設計,為元件偏壓穩定性之提升提供了一個解決方案。 In this research, we develop single channel and multi-channel nanowire amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). The influence of channel width and multi-channel geometry on the TFT performance was investigated. To achieve sub-micron channel widths, electron-beam lithography technology was used. The electron field-effect mobility of TFTs with 0.3 µm channel width is ~ 12 cm2/Vs, while that of TFTs with 40 µm channel width is ~8 cm2/Vs. An improvement of 50% in mobility was obtained, which may be attributed to the reduction of defects in the channel. The threshold voltages of nanowire TFTs increase slightly when the channel widths are reduced, which is probably resulted from the charge trapping at the surface states. The electron mobility of multi-channel TFTs composed of 0.3 µm nanowires is improved around 75%~80% compared to its effective single channel TFT. For multi-channel nanowire TFTs composed of two sub-micro scale sub-channels and two micro scale main-channels, their performance is similar to that of single channel TFTs with the same effective width except for threshold voltages. Larger threshold voltages were observed in the multi-channel TFTs, which may be due to larger surface-to-volume ratios. The reason that the electron mobility did not improve obviously was that the channel width of the main-channels being kept in micro scale. When the channel width is fixed, the devices with wide channel space have superior stability compared to the narrow-space one. The phenomenon is attributed to the multi-channel structure with relatively wide space which is suitable to assist the heat dissipation. In the gate-bias stress stability experiment, the TFT composed of wide main channels with narrow spacing and narrow sub-channels with wide spacing exhibits the best performance. After bias-stressed at VG = 10 V for 10000 s, its threshold voltage shift is only 0.43 V while the single-channel counterpart has a threshold voltage shift of 0.81 V. The characteristic trapping time of that of multi-channel TFT is around 3.03×1010 s and the β value is around 0.20 which is also better than its counterpart whose characteristic trapping time is around 7.98×108 s with the β value being around 0.20. By employing the multi-channel structure, threshold voltage shift is reduced around 53% and the characteristic trapping time is improved around 38 times. The result shows that the electrical bias-stress stability can be greatly improved by using a proper multi-channel geometry. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78507 |
DOI: | 10.6342/NTU201904050 |
全文授權: | 有償授權 |
顯示於系所單位: | 光電工程學研究所 |
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