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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳奕君(I-Chun Cheng) | |
| dc.contributor.author | Jiun-Yu Chen | en |
| dc.contributor.author | 陳俊瑜 | zh_TW |
| dc.date.accessioned | 2021-07-11T15:00:56Z | - |
| dc.date.available | 2022-08-23 | |
| dc.date.copyright | 2019-08-23 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-08-20 | |
| dc.identifier.citation | [1] K. Nomura, A. Takagi, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, 'Amorphous oxide semiconductors for high-performance flexible thin-film transistors,' Japanese Journal of Applied Physics, vol. 45, no. 5B, pp. 4303-4308, 2006, doi: 10.1143/jjap.45.4303.
[2] T. Sekitani, U. Zschieschang, H. Klauk, and T. Someya, 'Flexible organic transistors and circuits with extreme bending stability,' Nat Mater, vol. 9, no. 12, pp. 1015-22, 2010, doi: 10.1038/nmat2896. [3] S. D. Brotherton, J. R. Ayres, M. J. Edwards, C. A. Fisher, C. Glaister, J. P. Gowers, D. J. McCulloch, and M. Trainor, 'Laser crystallised poly-Si TFTs for AMLCDs,' Thin Solid Films, vol. 337, pp. 188-195, 1999, doi: 10.1016/S0040-6090(98)01176-6. [4] C. W. Chen, T. C. Chang, P. T. Liu, H. Y. Lu, K. C. Wang, C. S. Huang, C. C. Ling, and T. Y Tseng, 'High-performance hydrogenated amorphous-Si TFT for AMLCD and AMOLED applications,' IEEE Electron Device Letters, vol. 26, no. 10, pp. 731-733, 2005, doi: 10.1109/led.2005.855405. [5] H. Lebrun, F. Maurice, J. Magarino, and N. Szydlo, 'AMLCD with integrated drivers made with amorphous‐silicon TFTs,' Journal of the Society for Information Display, vol. 3, pp. 177-180, 1995, doi: 10.1889/1.1984963. [6] J. N. Sandoe, 'AMLCD on plastic substrates,' Journal of the Society for Information Display, vol. 29, pp. 293-296, 1998, doi: 10.1889/1.1833750. [7] J. E. Lilienfeld, 'Method and apparatus for controlling electric currents,' US pattern, 1930. [8] J. E. Lilienfeld, 'Amplifier for electric currents,' US pattern, 1932. [9] J. E. Lilienfeld, 'Device for controlling electric current,' US pattern, 1933. [10] P. K. Weimer, 'The TFT a new thin-film transistor,' Proceedings of the IRE, vol. 50, pp. 1462-1469, 1962, doi: 10.1109/JRPROC.1962.288190. [11] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, H. Hosono, 'Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor,' Science, vol. 300, pp. 1269-1272, 2003, doi: 10.1126/science.1083212. [12] T. Hirao, M. Furuta, T. Hiramatsu, T. Matsuda, C. Li, H. Furuta, H. Hokari, M. Yoshida, H. Ishii, and M. Kakegawa, 'Bottom-gate zinc oxide thin-film transistors (ZnO TFTs) for AM-LCDs,' IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3136-3142, 2008, doi: 10.1109/ted.2008.2003330. [13] H. Wang, M. Chan, S. Jagar, Y. Wang, and P.K. Ko, 'Submicron super TFTs for 3-D VLSI applications,' IEEE Electron Device Letters, vol. 21, pp. 439-441, 2000, doi: 10.1109/55.863104. [14] J. H. Choi, J. E. Pi, C. Y. Hwang, J. H. Yang, G. H. Kim, Y. H Kim, H. O. Kim, O. S Kwon, E. S. Park, and C. S. Hwang, 'Toward sub-micron oxide thin-film transistors for digital holography,' Journal of the Society for Information Display, vol. 25, no. 2, pp. 126-135, 2017, doi: 10.1002/jsid.535. [15] K. Fukuda, T. Sekine, R. Shiwaku, T. Morimoto, D. Kumaki, and S. Tokito, 'Free-standing organic transistors and circuits with sub-micron thicknesses,' Sci Rep, vol. 6, pp. 27450, 2016, doi: 10.1038/srep27450. [16] B. G. Streetman, Solid State Electronic Devices. Pearson, pp. 297, 2016. [17] L. Y. Su, H. Y. Lin, H. K. Lin, S. L. Wang, L. H. Peng, and J. J. Huang, 'Characterizations of amorphous IGZO thin-film transistors with low subthreshold swing,' IEEE Electron Device Letters, vol. 32, no. 9, pp. 1245-1247, 2011, doi: 10.1109/led.2011.2160931. [18] H. Hideo, 'New Frontiers Opened Up Through Function Cultivation in Transparent Oxides,' Handbook of Advanced Ceramics, pp. 455-487, 2013. [19] P. K. Nayak, M. N. Hedhili, D. Cha, and H. N. Alshareef, 'High performance In2O3 thin film transistors using chemically derived aluminum oxide dielectric,' Applied Physics Letters, vol. 103, no. 3, pp. 033518, 2013, doi: 10.1063/1.4816060. [20] C. C. Liu, M. L. Wu, K. C. Liu, S. H. Hsiao, Y. S. Chen, G. R. Lin, and J. J. Huang, 'Transparent ZnO thin-film transistors on glass and plastic substrates using post-sputtering oxygen passivation,' Journal of Display Technology, vol. 5, no. 6, pp. 192-197, 2009, doi: 10.1109/jdt.2008.2009321. [21] K. J. Saji and A. P. R. Mary, 'Tin oxide based p and n-type thin film transistors developed by rf sputtering,' ECS Journal of Solid State Science and Technology, vol. 4, no. 9, pp. Q101-Q104, 2015, doi: 10.1149/2.0091509jss. [22] N. Tiwari, R. N. Chauhan, P. T. Liu, and H. P. D. Shieh, 'Modification of intrinsic defects in IZO/IGZO thin films for reliable bilayer thin film transistors,' RSC Advances, vol. 6, no. 79, pp. 75693-75698, 2016, doi: 10.1039/c6ra13208a. [23] R. Upadhyay, S. Steudel, M.-P. Hung, A. K. Mandal, F. Catthoor, and M. Nag, 'Self-aligned amorphous indium-tin-zinc-oxide thin film transistors on polyimide foil,' ECS Journal of Solid State Science and Technology, vol. 7, no. 4, pp. 185-191, 2018, doi: 10.1149/2.0141804jss. [24] H. Yabuta, M. Sano, K. Abe, T. Aiba, T. Den, and H. Kumomi, 'High-mobility thin-film transistor with amorphous InGaZnO4 channel fabricated by room temperature rf-magnetron sputtering,' Applied Physics Letters, vol. 89, no. 11, pp. 112123, 2006, doi: 10.1063/1.2353811. [25] D. P. Heineck, B. R. McFarlane, and J. F. Wager, 'Zinc tin oxide thin-film-transistor enhancement/depletion inverter,' IEEE Electron Device Letters, vol. 30, no. 5, pp. 514-516, 2009, doi: 10.1109/led.2009.2017496. [26] P. C. Hsu, C. J. Hsu, C. H. Chang, S. P. Tsai, W. C. Chen, H. H. Hsieh, and C. C. Wu, 'Sputtering deposition of p-type SnO films with SnO2 target in hydrogen-containing atmosphere,' ACS Appl Mater Interfaces, vol. 6, no. 16, pp. 13724-9, Aug 27 2014, doi: 10.1021/am5031787. [27] C. T. Lee, C. C. Chen, and H. Y. Lee, 'Three dimensional-stacked complementary thin-film transistors using n-type Al:ZnO and p-type NiO thin-film transistors,' Sci Rep, vol. 8, no. 1, pp. 3968, Mar 5 2018, doi: 10.1038/s41598-018-22430-6. [28] J. Yu, G. Liu, A. Liu, Y. Meng, B. Shin, and F. Shan, 'Solution-processed p-type copper oxide thin-film transistors fabricated by using a one-step vacuum annealing technique,' Journal of Materials Chemistry C, vol. 3, no. 37, pp. 9509-9513, 2015, doi: 10.1039/c5tc02384j. [29] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, 'Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,' Nature, vol. 432, pp. 488-492, 2004, doi: 10.1038/nature03090. [30] J. T. Jang, J. Park, B. D. Ahn, D. M. Kim, S. J. Choi, H. S. Kim, and D. H. Kim., 'Study on the photoresponse of amorphous In-Ga-Zn-O and zinc oxynitride semiconductor devices by the extraction of sub-gap-state distribution and device simulation,' ACS Appl Mater Interfaces, vol. 7, no. 28, pp. 15570-7, 2015, doi: 10.1021/acsami.5b04152. [31] T. Kamiya and H. Hosono, 'Material characteristics and applications of transparent amorphous oxide semiconductors,' NPG Asia Materials, vol. 2, no. 1, pp. 15-22, 2010, doi: 10.1038/asiamat.2010.5. [32] K. Nomura, T. Kamiya, H. Ohta, T. Uruga, M. Hirano, and H. Hosono, 'Local coordination structure and electronic structure of the large electron mobility amorphous oxide semiconductor In-Ga-Zn-O: experiment and ab initio calculations,' Physical Review B, vol. 75, no. 3, 2007, doi: 10.1103/PhysRevB.75.035212. [33] T. Kamiya, K. Nomura, and H. Hosono, 'Origins of high mobility and low operation voltage of amorphous oxide tfts: electronic structure, electron transport, defects and doping,' Journal of Display Technology, vol. 5, no. 7, pp. 273-288, 2009, doi: 10.1109/jdt.2009.2021582. [34] M. Stewart, R.S. Howell, L. Pires, and M.K. Hatalis, 'Polysilicon tft technology for active matrix OLED displays,' IEEE Transactions on Electron Devices, vol. 48, pp. 845-851, 2001, doi: 10.1109/16.918227. [35] T. Serikawa, S. Shirai, A. Okamoto, and S. Suyama, 'Low-temperature fabrication of high-mobility poly-Si tfts for large-area LCDs,' IEEE Transactions on Electron Devices, vol. 36, no. 9, pp. 1929-1933, 1989, doi: 10.1109/16.34272. [36] C. C. Wu, S. D. Theiuss, G. Gu, M.H. Lu, J.C. Sturm, S. Wagner, and S.R. Forrest, 'Integration of organic LEDs and amorphous Si tfts onto flexible and lightweight metal foil substrates,' IEEE Electron Device Letters, vol. 18, no. 12, pp. 609-612, 1997, doi: 10.1109/55.644086. [37] N. Yamauchi, J.-J.J. Hajjar, and R. Reif, 'Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film,' IEEE Transactions on Electron Devices, vol. 38, pp. 55-60, 1991, doi: 10.1109/16.65736. [38] N. Yamauchi, J.-J.J. Hajjar, R. Reif, K. Nakazawa, and K. Tanaka, 'Characteristics of narrow-channel polysilicon thin-film transistors,' IEEE Transactions on Electron Devices, vol. 38, pp. 1967-1968, 1991, doi: 10.1109/16.119042. [39] D. N. Yaung, Y. K. Fang, K. C. Hwang, K. Y. Lee, K. H. Wu, J. J. Ho, C. Y. Chen, Y. J. Wang, M. S. Liang, J. Y. Lee, and S. G. Wuu 'Narrow width effects of bottom-gate polysilicon thin film transistors,' IEEE Electron Device Letters, vol. 19, pp. 429-431, 1998, doi: 10.1109/55.728902. [40] T. Noguchi, 'Appearance of single-crystalline properties in fine-patterned Si thin film transistors (TFTs) by solid phase crystallization (SPC),' Japanese Journal of Applied Physics, vol. 32, 1993, doi: 10.1143/JJAP.32.L1584. [41] S. Lee, Y. Chen, J. Kim, H. M. Kim, and J. Jang, 'Transparent AMOLED display driven by split oxide tft backplane,' Journal of the Society for Information Display, vol. 26, no. 3, pp. 164-168, 2018, doi: 10.1002/jsid.646. [42] M. J. Lee, S. J. Lee, W. Lee, and J. M. Myoung, 'Multiple parallel channels for improved resistance to repeated bending and unbending of amorphous indium–gallium–zinc oxide thin film transistors,' Microelectronic Engineering, vol. 179, pp. 7-12, 2017, doi: 10.1016/j.mee.2017.04.008. [43] J. H. Choi, J. H. Yang, J. E. Pi, C. Y. Hwang, K. Choi, H. O. Kim, O. S. Kwon, and C. S. Hwang, '1- µm Short-channel oxide thin-film transistors with triangular gate spacer,' IEEE Electron Device Letters, vol. 38, no. 10, pp. 1398-1400, 2017, doi: 10.1109/led.2017.2748102. [44] S. H. Choi and M. K. Han, 'Highly reliable multiple-channel IGZO thin-film transistors employing asymmetric spacing and channel width,' IEEE Electron Device Letters, vol. 34, no. 6, pp. 771-773, 2013, doi: 10.1109/led.2013.2256457. [45] M. Mativenga, D. Geng, J. H. Chang, T. J. Tredwell, and J. Jang, 'Performance of 5-nm a-IGZO TFTs with various channel lengths and an etch stopper manufactured by back UV exposure,' IEEE Electron Device Letters, vol. 33, no. 6, pp. 824-826, 2012, doi: 10.1109/led.2012.2191132. [46] S. H. Choi and M. K. Han, 'Effect of channel widths on negative shift of threshold voltage, including stress-induced hump phenomenon in InGaZnO thin-film transistors under high-gate and drain bias stress,' Applied Physics Letters, vol. 100, no. 4, 2012, doi: 10.1063/1.3679109. [47] H. W. Zan, T. C. Chang, P. S. Shih, D. Z. Peng, T. Y. Huang, and C. Y. Chang, 'Analysis of narrow width effects in polycrystalline silicon thin film transistors,' Japanese Journal of Applied Physics, vol. 42, no. Part 1, No. 1, pp. 28-32, 2003, doi: 10.1143/jjap.42.28. [48] H. Ohshima. and S. Morozumi, 'Future trends for tft integrated circuits on glass substrates,' International Technical Digest on Electron Devices Meeting, pp. 157-160, 1989, doi: 10.1109/IEDM.1989.74250. [49] T. Uchida, 'Present and future trend of electron device technology in flat panel display,' International Electron Devices Meeting, pp. 5-10, 1991, doi: 10.1109/IEDM.1991.235435. [50] A.O. Adan, K. Suzuki, H. Shibayama, and R. Miyake, 'A half-micron SRAM cell using a double-gated self-aligned polysilicon PMOS thin film transistor (TFT) load,' Digest of Technical Papers.1990 Symposium on VLSI Technology, pp. 19-20, 1990, doi: 10.1109/VLSIT.1990.110987. [51] H. J. Cho, F. Nemati, P. B. Griffin, and J. D. Plummer, 'A novel pillar DRAM cell for 4 Gbit and beyond,' Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39, 1998, doi: 10.1109/VLSIT.1998.689190. [52] R. E. Proano, R. S. Misage, and D. G. Ast, 'Development and electrical properties of undoped polycrystalline silicon thin-film transistors,' IEEE Transactions on Electron Devices, vol. 36, pp. 1915-1922, 1989, doi: 10.1109/16.34270. [53] L. A. Akers, M. M. E. Beguwala, and F. Z. Custode, 'Model of a narrow-width MOSFET including tapered oxide and doping encroachment,' IEEE Transactions on Electron Devices, vol. 28, pp. 1490-1495, 1981, doi: 10.1109/T-ED.1981.20635. [54] F. Qian, D. M. Kim, H. k. Park, and J.L. Sachitano, 'Inversion-mode MOSFET's in polycrystalline silicon thin films characterization and modeling,' IEEE Transactions on Electron Devices, vol. 35, pp. 2439-2449, 1987, doi: 10.1109/T-ED.1987.23333. [55] S. Shirai and T. Serikawa, 'Electrical analysis of high-mobility poly-Si tfts made from laser-irradiated sputtered Si Films,' IEEE Transactions on Electron Devices, vol. 39, pp. 450-452, 1992, doi: 10.1109/16.121707. [56] Y. C. Wu, T. C. Chang, P. T. Liu, C. W. Chou, C. H. Tu, J. C. Lou, and C. Y. Chang, 'Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization,' Applied Physics Letters, vol. 87, pp. 143504, 2005, doi: 10.1063/1.2076436. [57] H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin,Y. Wang, and P. K. Ko, 'Super Thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method,' IEEE Transactions on Electron Devices, vol. 47, pp. 1580-1586, 2000, doi: 10.1109/16.853034. [58] Y. C. Wu, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y. H. Tai, and C. Y. Chang, 'Effects of channel width on electrical characteristics of polysilicon tfts with multiple nanowire channels,' IEEE Transactions on Electron Devices, vol. 52, pp. 2343-2346, 2005, doi: 10.1109/TED.2005.856797. [59] S. Ju, A. Facchetti, Y. Xuan, J. Liu, F. Ishikawa, P. Ye, C. Zhou, T. J. Marks and D. B. Janes., 'Fabrication of fully transparent nanowire transistors for transparent and flexible electronics,' Nat Nanotechnol, vol. 2, no. 6, pp. 378-84, Jun 2007, doi: 10.1038/nnano.2007.151. [60] Z. Q. Yao, S. L. Liu, L. Zhang, B. He, A. Kumar, X. Jiang, W. J. Zhang, and G. Shao, 'Room temperature fabrication of p-channel Cu2O thin-film transistors on flexible polyethylene terephthalate substrates,' Applied Physics Letters, vol. 101, no. 4, pp. 042114, 012, doi: 10.1063/1.4739524. [61] Z. Xiao, F. Guojia, Y. Longyan, L. Meiya, G. Wenjie, and Z. Xingzhong, 'Top-gate low-threshold voltage p-Cu2O thin-film transistor grown on SiO2/Si substrate using a High-κ HfON gate dielectric,' IEEE Electron Device Letters, vol. 31, no. 8, pp. 827-829, 2010, doi: 10.1109/led.2010.2050576. [62] K. Matsuzaki, K. Nomura, H. Yanagi, T. Kamiya, M. Hirano, and H. Hosono, 'Epitaxial growth of high mobility Cu2O thin films and application to p-channel thin film transistor,' Applied Physics Letters, vol. 93, no. 20, pp. 202107, 2008, doi: 10.1063/1.3026539. [63] E. Fortunato, V. Figueiredo, P. Barquinha, E. Elamurugu, R. Barros, G. Gonçalves, S. K. Park, C. S Hwang, and R. Martins, 'Thin-film transistors based on p-type Cu2O thin films produced at room temperature,' Applied Physics Letters, vol. 96, no. 19, pp. 192102, 2010, doi: 10.1063/1.3428434. [64] E. Fortunato, R. Barros, P. Barquinha, V. Figueiredo, S. H. Ko Park, C. S. Hwang, and R. Martins., 'Transparent p-type SnOx thin film transistors produced by reactive rf magnetron sputtering followed by low temperature annealing,' Applied Physics Letters, vol. 97, no. 5, pp. 052105, 2010, doi: 10.1063/1.3469939. [65] H. N. Lee, H. J. Kim, and C. K. Kim, 'p-channel tin monoxide thin film transistor fabricated by vacuum thermal evaporation,' Japanese Journal of Applied Physics, vol. 49, no. 2, pp. 020202, 2010, doi: 10.1143/jjap.49.020202. [66] L. Y. Liang, Z. M. Liu, H. T. Cao, W. Y. Xu, X. L. Sun, H. L. and K. Cang, 'The structural, optical and electrical properties of Y-doped SnO thin films and their p-type tft application,' Journal of Physics D: Applied Physics, vol. 45, no. 8, pp. 085101, 2012, doi: 10.1088/0022-3727/45/8/085101. [67] Y. Ogo, H. Hiramatsu, K. Nomura, H. Yanagi, T. Kamiya, M. Hirano, and H. Hosono, 'p-channel thin-film transistor using p-type oxide semiconductor, SnO,' Applied Physics Letters, vol. 93, no. 3, pp. 032113, 2008, doi: 10.1063/1.2964197. [68] H. Yabuta, N. Kaji, R. Hayashi, H. Kumomi, K. Nomura, T. Kamiya, M. Hirano, and H. Hosono, 'Sputtering formation of p-type SnO thin-film transistors on glass toward oxide complimentary circuits,' Applied Physics Letters, vol. 97, no. 7, pp. 072111, 2010, doi: 10.1063/1.3478213. [69] J. A. Caraveo-Frescas, P. K. Nayak, H. A. Al-Jawhari, D. B. Granato, U. Schwingenschlogl, and H. N. Alshareef, 'Record mobility in transparent p-type tin monoxide films and devices by phase engineering,' ACS Nano, vol. 7, no. 6, pp. 5160-7, 2013, doi: 10.1021/nn400852r. [70] J. A. Caraveo-Frescas and H. N. Alshareef, 'Transparent p-type SnO nanowires with unprecedented hole mobility among oxide semiconductors,' Applied Physics Letters, vol. 103, no. 22, pp. 222103, 2013, doi: 10.1063/1.4833541. [71] K. Watanabe and T. Asano, 'Self-heating of laterally grown polycrystalline silicon thin-film transistor,' Japanese Journal of Applied Physics, vol. 48, no. 3, pp. 03B005, 2009, doi: 10.1143/jjap.48.03b005. [72] M. Fujii, H. Yano, T. Hatayama, Y. Uraoka, T. Fuyuki, J. S. Jung and J. Y. Kwon, 'Thermal analysis of degradation in Ga2O3–In2O3–ZnO thin-film transistors,' Japanese Journal of Applied Physics, vol. 47, no. 8, pp. 6236-6240, 2008, doi: 10.1143/jjap.47.6236. [73] H. H. Hsu, C. Y. Chang, C. H. Cheng, S. H. Yu, C. Y. Su, and C. Y. Su, 'Fully room-temperature IGZO thin film transistors adopting stacked gate dielectrics on flexible polycarbonate substrate,' Solid-State Electronics, vol. 89, pp. 194-197, 2013, doi: 10.1016/j.sse.2013.08.009. [74] D. Kang, I. Song, C. Kim, and Y. Park, 'Effect of Ga/In ratio on the optical and electrical properties of GaInZnO thin films grown on SiO2/Si substrates,' Applied Physics Letters, vol. 91, pp. 091910, 2007, doi: 10.1063/1.2773952. [75] J. Triska, J. F. Conley, R. Presley, and J. F. Wager, 'Bias stress stability of zinc-tin-oxide thin-film transistors with Al2O3 gate dielectrics,' Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 28, no. 4, pp. C5I1-C5I6, 2010, doi: 10.1116/1.3455494. [76] A. Suresh and J. F. Muth, 'Bias stress stability of indium gallium zinc oxide channel based transparent thin film transistors,' Applied Physics Letters, vol. 92, no. 3, pp. 033502, 2008, doi: 10.1063/1.2824758. [77] K. Nomura, T. Kamiya, M. Hirano, and H. Hosono, 'Origins of threshold voltage shifts in room-temperature deposited and annealed a-In–Ga–Zn–O thin-film transistors,' Applied Physics Letters, vol. 95, no. 1, pp. 013502, 2009, doi: 10.1063/1.3159831. [78] M. E. Lopes, H. L. Gomes, M. C. R. Medeiros, P. Barquinha, L. Pereira, E. Fortunato, R. Martins, and I. Ferreira, 'Gate-bias stress in amorphous oxide semiconductors thin-film transistors,' Applied Physics Letters, vol. 95, no. 6, pp. 063502, 2009, doi: 10.1063/1.3187532. [79] J. M. Lee, I. T. Cho, J. H. Lee, and H. I. Kwon, 'Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors,' Applied Physics Letters, vol. 93, no. 9, pp. 093504, 2008, doi: 10.1063/1.2977865. [80] Y. W. Heo, K. M. Cho, S. Y. Sun, S. Y. Kim, J. H. Lee, and J. J. Kim, 'Effects of channel dimensions on performance of a-InGaZnO4 thin-film transistors,' Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 29, no. 2, pp. 021203, 2011, doi: 10.1116/1.3556921. [81] H. Oh, K. Cho, S. Park, and S. Kim, 'Electrical characteristics of bendable a-IGZO thin-film transistors with split channels and top-gate structure,' Microelectronic Engineering, vol. 159, pp. 179-183, 2016, doi: 10.1016/j.mee.2016.03.044. [82] L. Liu, R. Liang, B. Shan, J. Xu, and J. Wang, 'Technology demonstration of a novel poly-Si nanowire thin film transistor,' Chinese Physics B, vol. 25, no. 11, pp. 118504, 2016, doi: 10.1088/1674-1056/25/11/118504. [83] T. K. Kang and Y. Y. Yang, 'Poly-Si nanowire tft with raised source/drain and nitride spacer,' IEEE Transactions on Electron Devices, vol. 60, no. 7, pp. 2415-2418, 2013, doi: 10.1109/ted.2013.2262075. [84] S. Puckett, R. Pareta, and T. J. Webster, 'Nano rough micron patterned titanium for directing osteoblast morphology and adhesion,' International Journal of Nanomedicine, vol. 3, pp. 229-241, 2008, doi: pubmed/18686782. [85] M. Leskelä, J. Niinistö, and M. Ritala, 'Atomic Layer Deposition,' in Comprehensive Materials Processing, 2014, pp. 101-123, doi: 10.1016/B978-0-08-096532-1.00401-5. [86] M. Kariniemi, J. Niinistö, T. Hatanpää, M. Kemell, T. Sajavaara, M. Ritala, and M. Leskelä, 'Plasma-enhanced atomic layer deposition of silver thin films,' Chemistry of Materials, vol. 23, no. 11, pp. 2901-2907, 2011, doi: 10.1021/cm200402j. [87] M. Meyyappan, L. Delzeit, A. Cassell and D. Hash, 'Carbon nanotube growth by PECVD: a review,' Plasma Sources Science and Technology, vol. 12, pp. 205-216, 2003, doi: 10.1088/0963-0252/12/2/312. [88] G. Bräuer, 'Magnetron sputtering,' in Comprehensive Materials Processing, 2014, pp. 57-73, doi: 10.1016/B978-0-08-096532-1.00403-9. [89] P. S. McLeod, 'Planar magnetron sputtering method and apparatus,' US pattern, 1974. [90] L. Y. Chen, W. H. Chen, J. J. Wang, F. C. N. Hong, and Y. K. Su, 'Hydrogen-doped high conductivity ZnO films deposited by radio-frequency magnetron sputtering,' Applied Physics Letters, vol. 85, no. 23, pp. 5628-5630, 2004, doi: 10.1063/1.1835991. [91] C. Mack, 'Fundamental principles of optical lithography: the science of microfabrication,' John Wiley & Sons, Ltd, pp. 13, 2007, doi: 10.1002/9780470723876. [92] University of North Texas, 'JEOL JSM-7001F scanning electron microscope,' https://nanofabrication.unt.edu/jeol-jsm-7001f-scanning-electron-microscope, 2019. [93] JEOL, 'JEOL JSM 6700F SEM Users Manual,' JEOL. [94] L. Sun, H. Liu, J. Huang, X. Ye, Q. Cheng, X. Zhou, F. Wang, X. Jiang, and W. Wu, 'The effect of rie-modified surface contamination on optical performance of fused silica,' Proceedings of SPIE - The International Society for Optical Engineering, vol. 8786, pp. 87860, 2013, doi : 10.1117/12.2020381. [95] Phillips, 'Basic XRD Theory,' https://engineering.jhu.edu/labs/wp-content/uploads/sites/76/2016/04/Phillips-Basic-XRD-Theory.pdf, pp. 5-5, 2019. [96] W. F. S. John, F. Moulder, P. E. Sobol, K. D. Bomben, 'Handbook of x-ray photoelectron spectroscopy,' pp. 89, 1992. [97] A. V. Gelatos and J. Kanicki, 'Bias stress‐induced instabilities in amorphous silicon nitride/hydrogenated amorphous silicon structures: is the ‘‘carrier‐induced defect creation’’ model correct?,' Applied Physics Letters, vol. 57, no. 12, pp. 1197-1199, 1990, doi: 10.1063/1.103484. [98] F. R. Libsch and J. Kanicki, 'Bias‐stress‐induced stretched‐exponential time dependence of charge injection and trapping in amorphous thin‐film transistors,' Applied Physics Letters, vol. 62, no. 11, pp. 1286-1288, 1993, doi: 10.1063/1.108709. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/78507 | - |
| dc.description.abstract | 本研究致力於開發奈米線單通道與多通道氧化銦鎵鋅薄膜電晶體，探討通道寬度及結構組成對元件電特性的影響。研究中使用電子束微影技術來達到次微米級通道寬度。通道寬度為0.3 µm之薄膜電晶體，其電子遷移率約為12 cm2/Vs，相較於寬度為40 µm之元件的電子遷移率8 cm2/Vs，提升了~50%，其成因可能是通道缺陷數量的減少。奈米線薄膜電晶體其臨界電壓隨著通道寬度的縮小，呈現上升的趨勢，造成此現象的原因可能來自於通道表面電荷空乏較為嚴重。
本研究另一個重點在於多通道奈米線結構設計與其特性表現探討。由0.3 µm寬奈米線所組成之多通道結構，相較其等效單通道結構，電子遷移率提升約75%至80%。由四條微米與次微米級寬度組成之多通道結構薄膜電晶體，其電特性表現，相較於等效單通道結構，除因次通道由奈米線組成而造成臨界電壓略為上升以外，並沒有顯著的差異。四條多通道結構薄膜電晶體，電子遷移率未被明顯提升的原因，為其主通道寬度停留在微米等級。固定通道寬度、改變通道間距時，寬間距的元件偏壓穩定性表現較窄間距佳，此現象為具有較大通道間距、可以協助元件散熱之多通道結構設計所貢獻。在偏壓穩定性測試下，主通道寬度較寬、間距較窄；次通道寬度較窄、間距較寬的多通道結構，在施加 VG = 10 V偏壓 10000 秒後，其臨界電壓偏移僅0.43 V，元件特徵捕獲時間約為3.03×1010秒、β值約為0.20；相較等效單通道結構臨界電壓偏移量0.81 V，特徵捕獲時間約為7.98×108秒、β值約為0.20，其穩定性大幅提升，臨界電壓偏移量減少約53%，特徵捕獲時間約得以提升38倍，多通道結構設計，為元件偏壓穩定性之提升提供了一個解決方案。 | zh_TW |
| dc.description.abstract | In this research, we develop single channel and multi-channel nanowire amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). The influence of channel width and multi-channel geometry on the TFT performance was investigated. To achieve sub-micron channel widths, electron-beam lithography technology was used. The electron field-effect mobility of TFTs with 0.3 µm channel width is ~ 12 cm2/Vs, while that of TFTs with 40 µm channel width is ~8 cm2/Vs. An improvement of 50% in mobility was obtained, which may be attributed to the reduction of defects in the channel. The threshold voltages of nanowire TFTs increase slightly when the channel widths are reduced, which is probably resulted from the charge trapping at the surface states.
The electron mobility of multi-channel TFTs composed of 0.3 µm nanowires is improved around 75%~80% compared to its effective single channel TFT. For multi-channel nanowire TFTs composed of two sub-micro scale sub-channels and two micro scale main-channels, their performance is similar to that of single channel TFTs with the same effective width except for threshold voltages. Larger threshold voltages were observed in the multi-channel TFTs, which may be due to larger surface-to-volume ratios. The reason that the electron mobility did not improve obviously was that the channel width of the main-channels being kept in micro scale. When the channel width is fixed, the devices with wide channel space have superior stability compared to the narrow-space one. The phenomenon is attributed to the multi-channel structure with relatively wide space which is suitable to assist the heat dissipation. In the gate-bias stress stability experiment, the TFT composed of wide main channels with narrow spacing and narrow sub-channels with wide spacing exhibits the best performance. After bias-stressed at VG = 10 V for 10000 s, its threshold voltage shift is only 0.43 V while the single-channel counterpart has a threshold voltage shift of 0.81 V. The characteristic trapping time of that of multi-channel TFT is around 3.03×1010 s and the β value is around 0.20 which is also better than its counterpart whose characteristic trapping time is around 7.98×108 s with the β value being around 0.20. By employing the multi-channel structure, threshold voltage shift is reduced around 53% and the characteristic trapping time is improved around 38 times. The result shows that the electrical bias-stress stability can be greatly improved by using a proper multi-channel geometry. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-11T15:00:56Z (GMT). No. of bitstreams: 1 ntu-108-R06941051-1.pdf: 22435157 bytes, checksum: d3dec4ed84585ccb75dd85ef03ecfadb (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 致謝 i
摘要 iii Abstract v 圖目錄 x 表目錄 xxvi 第一章 緒論 1 1.1 薄膜電晶體發展與研究背景 1 1.2 研究動機與目的 3 1.3 論文架構 5 第二章 理論與文獻回顧 7 2.1 金屬氧化物半導體薄膜電晶體介紹 7 2.1.1 金屬氧化物半導體薄膜電晶體之元件結構 7 2.1.2 金屬氧化物半導體薄膜電晶體之工作原理 9 2.1.3 金屬氧化物半導體薄膜電晶體之特徵參數計算 11 2.1.4 金屬氧化物半導體薄膜電晶體閘極介電層介電能力分析 18 2.2 氧化物半導體介紹 18 2.2.1 氧化銦鎵鋅半導體介紹與發展 20 2.2.2 氧化銦鎵鋅材料之物理特性 21 2.3 奈米線單通道與多通道薄膜電晶體介紹 26 2.4 單通道及多通道氧化銦鎵鋅薄膜電晶體介紹與文獻回顧 49 2.4.1 微米級通道寬度氧化銦鎵鋅薄膜電晶體 49 2.4.2 奈米級通道寬度氧化銦鎵鋅薄膜電晶體 59 第三章 實驗方法與步驟 71 3.1 薄膜沉積方法 71 3.1.1 電子束蒸鍍系統 71 3.1.2 原子層沉積系統 73 3.1.3 電漿輔助式化學氣相沉積系統 74 3.1.4 射頻磁控濺鍍系統 75 3.2 微影製程 78 3.2.1 光微影技術 78 3.2.2 場發射掃描式電子顯微鏡 82 3.2.3 電子束微影技術 83 3.3 蝕刻製程 87 3.3.1 濕式蝕刻製程 87 3.3.2 乾式蝕刻製程 88 3.4 單通道與多通道奈米線氧化銦鎵鋅薄膜電晶體製程 90 3.4.1 定位座標光罩設計 90 3.4.2 電子束微影單通道與多通道遮罩設計 92 3.4.3 單通道與多通道奈米線氧化銦鎵鋅薄膜電晶體製造流程 97 3.5 金屬-絕緣層-金屬電容結構製備流程 105 3.6 薄膜分析與元件特性量測 105 3.6.1 X 光繞射分析 105 3.6.2 薄膜電晶體特性量測方法 106 3.6.3 薄膜電晶體偏壓穩定性量測方法 107 第四章 實驗結果與討論 108 4.1 二氧化鉿絕緣層之介電性質分析 108 4.2 氧化銦鎵鋅薄膜分析 109 4.2.1 氧化銦鎵鋅薄膜結晶分析 109 4.2.2 氧化銦鎵鋅薄膜成分分析 110 4.3 氧化銦鎵鋅薄膜電晶體元件分析 112 4.3.1 氧化銦鎵鋅薄膜電晶體元件特性分析 113 4.4 單通道奈米線氧化銦鎵薄膜電晶體元件分析 119 4.4.1 奈米線單通道之場發射掃描式電子顯微鏡尺寸鑑定 120 4.4.2 通道寬度於次微米等級對電晶體電特性表現影響分析 122 4.4.3 通道長度對電晶體電特性表現影響分析 152 4.5 多通道奈米線氧化銦鎵薄膜電晶體電特性分析與偏壓穩定性分析 170 4.5.1 氧化銦鎵鋅奈米線通道數量對電晶體偏壓穩定性分析 170 4.5.2 多通道以及等效單通道氧化銦鎵鋅奈米線薄膜電晶體通道結構光學顯微鏡影像圖 182 4.5.3 多通道以及等效單通道氧化銦鎵鋅奈米線薄膜電晶體偏壓穩定性分析 186 第五章 結論與未來展望 210 5.1 結論 210 5.2 未來展望 212 參考文獻 213 | |
| dc.language.iso | zh-TW | |
| dc.subject | 奈米線電晶體 | zh_TW |
| dc.subject | 偏壓穩定性 | zh_TW |
| dc.subject | 多通道結構 | zh_TW |
| dc.subject | 電子束微影 | zh_TW |
| dc.subject | 薄膜電晶體 | zh_TW |
| dc.subject | n型氧化物半導體 | zh_TW |
| dc.subject | 非晶氧化銦鎵鋅 | zh_TW |
| dc.subject | gate bias stress stability | en |
| dc.subject | amorphous indium-gallium-zinc-oxide (a-IGZO) | en |
| dc.subject | n-type oxide semiconductors | en |
| dc.subject | electron-beam lithography (EBL) | en |
| dc.subject | nanowire transistors | en |
| dc.subject | multi-channel structures | en |
| dc.title | 多通道奈米線氧化銦鎵鋅薄膜電晶體之研究 | zh_TW |
| dc.title | Multi-channel nanowire InGaZnO Thin-Film Transistors | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳建彰(Jian-Zhang Chen),吳育任(Yuh-Renn Wu),徐振哲(Cheng-Che Hsu),吳肇欣(Chao-Hsin Wu) | |
| dc.subject.keyword | 非晶氧化銦鎵鋅,n型氧化物半導體,薄膜電晶體,電子束微影,奈米線電晶體,多通道結構,偏壓穩定性, | zh_TW |
| dc.subject.keyword | amorphous indium-gallium-zinc-oxide (a-IGZO),n-type oxide semiconductors,electron-beam lithography (EBL),nanowire transistors,multi-channel structures,gate bias stress stability, | en |
| dc.relation.page | 226 | |
| dc.identifier.doi | 10.6342/NTU201904050 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
| 顯示於系所單位： | 光電工程學研究所 | |
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