動態隨機存取記憶體分析及指叉式背電極異質接面太陽能電池模擬

Abstract

人工智慧、物聯網、自駕車都需要快速的運算效能，而運算的速度被動態隨機存取記憶體所影響，這驅動了動態隨機存取記憶體的需求成長以及持續的微縮。另外，由於全球暖化日益嚴重，屬於綠色能源的太陽能也被積極發展，目前全球各個團隊都試圖將太陽能電池的效率提高以降低單位電費售價。在本論文當中，將會對於動態隨機存取記憶體以及指叉式背電極異質接面太陽能電池進行深入的探討。 動態隨機存取記憶體的基本存取資料的架構為一個電晶體配上一個電容，其中電容用來做為資料的儲存，而電晶體用來控制資料的讀取。在論文中，對於凹槽通道存取電晶體的幾何結構、摻雜濃度進行模擬分析。隨著閘極的凹槽深度增加，電晶體的通道長度也跟著提升，透過增加閘極的凹槽深度可以避免傳統平面型電晶體會遇到的短通道效應。另外，透過三維模擬探討在元件前後施加材料對元件的效能影響，結果顯示藉由施加材料可以有效提升汲極電流。 為了有效保存資料，高電容值及低漏電的電容在動態隨機存取記憶體是被要求的。研究中使用原子層沉積技術成長高介電係數材料之電容，透過二氧化鋯作為主要提供電容值的材料，並在二氧化鋯中間成長一層氧化鋁做為漏電流之阻擋層，以此結構設計得到優異的電容表現。另外，藉由使用鉑做為電容的下電極，成功改善電容電壓特性曲線以及電流電壓特性曲線的非對稱性。最後，將二氧化鈦加入介電層當中，成功將電容等效厚度降至0.75 奈米。 指叉式背電極異質接面太陽能電池在效率上有著優良的表現，其背電極的設計可以增加吸光量，本質非晶矽之異質接面的使用可以增加開路電壓。本論文中使用三維Sentaurus TCAD模擬探討太陽能電池之幾何結構、摻雜濃度、表面複合速率對於太陽能電池之影響。透過在基板的正面施加額外的摻雜，太陽能電池的效率有顯著的提升。另外，藉由調控背電極之射極比率，可以達到載子蒐集的最佳化。最後，提出矩陣型之背電極，成功降低太陽能電池之效率對於射極比率的敏感度。

In this thesis, we will discuss dynamic random access memory (DRAM) and interdigitated back contact silicon heterojunction (IBC-SHJ) solar cells. The speed of computing is affected by DRAM which is main memory in the computer. Artificial intelligence (AI), internet of things (IoT) and autonomous car need high speed computing to achieve their function, and it becomes a driving force of DRAM scale down. In addition, solar power which is a kind of renewable energy is developed to solving the global warming problem, and many research teams try to increase the efficiency of solar cells to reduce the electricity price. DRAM unit cell includes one transistor and one capacitor (1T1C). The data is stored by capacitor, and the function of transistor is control of both reading data and writing data. In this thesis, the geometry and doping concentration of recessed channel array transistor (RCAT) are investigated by Sentaurus TCAD simulation. The channel length of RCAT increases with increasing word line depth, and short channel effect can be overcome due to larger channel length. In addition, the influence of coverage material is investigated by 3D simulation, and the result shows that the drain current can be increased by coverage. High capacitance and low leakage current are required in DRAM to make sure data storage. In this thesis, atomic layer deposition (ALD) is used to fabricate high-k metal-insulator-metal (MIM) capacitors. ZrO2/Al2O3/ZrO2 (ZAZ) dielectric layers have been adopted due to large dielectric constant of ZrO2 and large band gap of Al2O3. Asymmetric J-V curve and C-V curve are improved by platinum bottom electrode. Finally, capacitance equivalent thickness (CET) is decreased to 0.75 nm by using titanium dioxide. Interdigitated back contact silicon heterojunction solar cells have the advantage of high conversion efficiency. The interdigitated back contact can reduce the front reflection, and the heterojunction with intrinsic thin layer can enhance the open-circuit voltage. In this thesis, the geometry, surface recombination rate and doping concentration of IBC-SHJ solar cells are investigated by 3D Sentaurus TCAD simulation. The additional front surface doping is adopted and reduces the influence of surface recombination. Furthermore, the emitter ratio of IBC-SHJ solar cells is optimized to increase the collection of carrier. Finally, we propose rectangular array back contact and successfully reduce the sensitivity of efficiency to emitter ratio.